Week In Review: Design, Low Power

Tools & IP
Codasip debuted two new customizable low power embedded RISC-V processor cores. To support embedded AI applications, the L31/L11 cores run Google’s TensorFlowLite for Microcontrollers. Codasip Studio tools can be used to customize for specific system, software, and application requirements. Licensing the CodAL description of a Codasip RISC-V core grants customers a full architecture license.

Arm unveiled a new automotive image signal processor for ADAS. The Mali-C78AE ISP is able to process data from up to four real-time or 16 virtual cameras, includes noise reduction technology and dynamic range management, and enables camera sensors to be dual-purpose by downscaling and color-translating the outputs of sensors optimized for machine vision to create images adapted to the human eye. Designed to meet ISO 26262 ASIL B functional safety requirements and prevent or detect faults in a single camera frame that may result in incorrectly processed frame data, it has over 380 fault detection circuits, continuous built in self-test, and can detect sensor and hardware faults of connected cameras. It can be combined with Cortex-A78AE and Mali-G78AE to provide a full ADAS vision pipeline. Mobileye will use the ISP in the next generation of its EyeQ technology.

Vtool and Concept Engineering collaborated to connect the companies’ tools to provide a debug solution for both design and testbench code simultaneously. The integrated solution enables navigation from advanced log file displays to capable waveform analysis tools and vice versa, with the ability to simultaneously focus on the status of the design and verification environment at any time-point. “We have been working together with Concept Engineering to combine the advanced visualization capabilities of our Cogita technology with Concept Engineering’s broadly used RTLvision and StarVision PRO to solve the increasing challenges of chip design complexities,” said Hagai Arbel, CEO, Vtool. “We are proud to have established this unique synergy that will shorten debug cycles, a significant component of chip development today, while increasing the confidence of first-time-right silicon.”

Cadence and Dassault Systèmes teamed up to combine Dassault Systèmes’ 3DEXPERIENCE platform with the Cadence Allegro platform in a joint solution for multidiscipline modeling, simulation, and optimization of electronic systems. The collaborative ‘virtual twin experiences’ integrate capabilities for electronic and mechanical product lifecycle management, business process analytics, and electronic systems development, engineering, and traceability to provide a complete, real-time view of electrical and mechanical simulation, manufacturing, and supply chain execution for the product lifecycle.

CHIPS Alliance established the FOSS Flow For FPGA (F4PGA) Workgroup to drive open source tooling, IP, and research efforts for FPGAs. The initial F4PGA projects are focused around the free and open source FPGA toolchain formerly known as SymbiFlow, as well as the FPGA Interchange Format, which is designed to enable interoperability between open and closed source FPGA toolchains. “FPGAs are essential for a wide variety of low-latency compute use cases, from telecoms to space applications and beyond. This new F4PGA toolchain will enable a software-driven approach to building FPGA gateware, making code integration easier than ever,” said Rob Mains, General Manager at CHIPS Alliance. “Under the umbrella of the CHIPS Alliance, this workgroup will help unite current FPGA efforts so academia and industry leaders can collaborate on accelerating open FPGA innovation.”

Ansys reported fourth quarter and full year 2021 financial results. For the fourth quarter, revenue was $655.7 million, an increase of 5.1% compared to the same quarter last year. For the 2021 fiscal year, revenue was $1,906.7 million, up 13.4% compared to 2020. “Q4 capped an outstanding year and demonstrated the strength of our business model as we beat our financial guidance across all key metrics for both the quarter and the full-year,” said Nicole Anasenes, Ansys CFO. “In FY 2021, our growth was wide-ranging across geographies and industries, and we achieved new company records across key financial metrics, including ACV, revenue and operating cash flow. We are entering 2022 with momentum and a strong backlog driven by the broad-based strength of our product portfolio. This bolsters our confidence in our 2022 guidance, which exceeds the 2022 ACV target of $2 billion outlined at our 2019 investor day.”

Cadence reported fourth quarter and full year 2021 financial results. For the fourth quarter, revenue was $773 million, up 1.7% compared to the same period last year. For the full year, revenue was $2,988 million, an increase of 11.4% compared to the previous year. “Steady growth in our three year revenue growth CAGR continues to drive operating margin expansion, and the quality of those improvements in earnings are showing up in our operating cash, which hit $1.1 billion for the year,” said John Wall, senior vice president and chief financial officer. “I am pleased that we can build on 2021 with a strong outlook for 2022.”

Wireless & networking
Infineon announced new antenna tuning switches suitable for sub-7.2 GHz New Radio (NR) applications, supporting both 4G and 5G in smartphones, notebooks, wearables, VR headsets, smart home, and other cellular applications. They are available in both medium and high RF voltage.

Renesas introduced two 2.4 GHz RF transceiver technologies that support Bluetooth Low Energy. The first is a matching circuit technology that covers a wide impedance range and enables the IC to match a variety of antenna and board impedances without an external impedance-matching circuit. The second is a signal correction technology for locally generated reference signals that uses a small circuit to self correct inconsistencies in the circuit elements and variations in surrounding conditions without calibration. In a prototype, Renesas was able to reduce the circuit area including the power supply to 0.84 mm2.

Keysight’s S8705A RF/RRM and DVT Conformance Toolset was used to gain PTCRB validation of test cases that accelerate certification of 5G devices that support carrier aggregation (CA) technology using frequency range 1 (FR1) spectrum. The new test cases enable chipset and device makers to verify that 5G NR designs comply to the latest 3GPP Release 15 specifications in terms of RF performance. “This PTCRB test case validation is essential to the global 5G device ecosystem that needs to support high downlink data speeds using frequency bands in widely available sub-6GHz spectrum,” said Muthu Kumaran, general manager of Keysight’s device validation solutions business.

Arm updated on the projects underway at its Arm 5G Solutions Lab, a collaboration with 18 other companies across the 5G ecosystem. Among the projects is a 5G network in a box for microcell deployments based on open RAN designs. It has a multicore design to allow DSP to be performed on general-purpose silicon and core and RAN functions to be combined into a single server. Another is 5G small cells for smart city deployments that support both sub-6 GHz and mmWave.

Intel launched two new Xeon D processors. Targeting the software-defined network and edge, they include AI and crypto acceleration, built-in Ethernet, support for Intel Time Coordinated Computing (Intel TCC) and Time Sensitive Networking (TSN), and industrial-class reliability. Intel also introduced several new mobile processors, the 12th Gen Intel Core P-Series and U-Series. The two new families target thin, lightweight laptops and have up to 14 cores with up to 70% faster multi-thread performance compared to the previous generation. Additionally, Intel unveiled its roadmap for products from 2022 to 2024.

CEVA announced its second generation 5G platform architecture. PentaG2 is a hardware/software IP platform that integrates low power DSPs with specialized programmable accelerators for optimal modem processing chains, delivering up to a 4X improvement in power efficiency versus its predecessor. It supports multiple use cases, from RedCap, NR-Sidelink and C-V2X, through to high end eMBB for handsets, CPE/FWA Terminals and mmWave and URLLC for XR headsets.

Keysight and Telefonica validated an open radio access network (RAN) xHaul transport link. xHaul is a unified fronthaul and backhaul networking infrastructure. It creates a common packet-based transport network for flexible and software-defined reconfiguration of networking elements in a service-oriented unified management framework.

MaxLinear uncorked an SoC for 4G/5G Open RAN radio units (RU). It includes an RF Transceiver supporting up to 8 transmitters, 8 receivers, and 2 feedback receivers, a Digital Front End (DFE) supporting digital up-conversion (DUC) and digital down-conversion (DDC) of component carriers, low PHY Baseband Processor supporting 5G, 4G, and NB-IoT air interfaces, and Fronthaul Interface compliant with O-RAN Alliance Split 7.2x.

Samsung Electronics and SK Telecom successfully completed a 5G-4G SA Option 4 (NE-DC, New Radio–E-UTRAN Dual Connectivity) trial in SK Telecom 5G Standalone (5G SA) commercial network. SA Option 4 is a dual connectivity technology that connects both 5G and 4G radios to a 5G Core in advanced 5G SA mode, enabling operators to increase reliability and maximize their current network resources.

Power devices
Infineon expanded its portfolio of isolated EiceDRIVER Enhanced gate drivers with the F3 Enhanced (1ED332x) family, which implements protection to prevent destructive short-circuit events for both conventional power switches, such as IGBTs, as well as wide-bandgap devices. The single-channel isolated gate driver offers high common-mode transient immunity (CMTI) of up to 300 kV/us and typical output currents of up to 8.5 A. It targets applications such as for industrial drives, solar systems, electric vehicle charging, energy storage systems, and commercial air conditioning.

Infineon announced a new 2-channel, analog input, class D audio amplifier multichip module (MCM). MERUS MA5332MS integrates a dual-channel PWM controller, a high-voltage gate driver, and four low R DS(ON) MOSFETs. Due to its very low R DS(on) class D output stage (24.4 mΩ typical), it can deliver 2 x 100 W at 4 Ω operating heatsink-free or 2 x 200 W at 4 Ω with a small 8°C/W heatsink. It targets consumer products such as soundbars as well as professional applications.

Memory
Kioxia started sampling Universal Flash Storage (UFS) embedded flash memory devices supporting MIPI M-PHY v5.0. Using the company’s BiCS FLASH 3D flash memory, it is available in 128GB, 256GB, and 512GB capacities. They have a theoretical interface speed of up to 23.2Gbps per lane (x2 lanes = 46.4Gpbs) in HS-GEAR5 mode. The UFS memory targets mobile devices such as high-end smartphones.

Quantum computing
DARPA announced the Underexplored Systems for Utility-Scale Quantum Computing (US2QC) program with the aim of determining if an underexplored approach to quantum computing is capable of achieving utility-scale operation much faster than conventional predictions. Complementary to the agency’s quantum benchmarking program, US2QC is focused on verifying and validating system, component, and sub-system designs for a proposed fault-tolerant quantum computer. “If there’s an underexplored area of quantum computing showing promise for a faster breakthrough than we previously expected, we want to explore it immediately and thoroughly verify and validate the approach’s viability,” said Joe Altepeter, US2QC program manager in DARPA’s Defense Sciences Office. “If a company or an organization thinks they can make a truly useful, really big, fault-tolerant quantum computer, we want to have a conversation with them. We would like them to show us exactly why they’re convinced their machine is going to be revolutionary in the near future, and we want to work collaboratively with them, pay for additional experts to embed with their team, and help advance bold concepts that withstand rigorous testing.”

Super.tech released SupermarQ, an application-centric benchmarking suite for quantum computers. The suite aims to measure a machine’s performance on a range of applications that mirror real-world problems in a variety of domains such as finance, chemistry, energy, and encryption. Instead of combining different aspects of performance into a single number, it aims to show how well a device or architecture can complete a given task, such as optimization, simulation, or error correction. “Our approach illustrates the importance of matching the device architecture to the use-case,” said said Pranav Gokhale, Super.tech co-founder and CEO.

People
Keysight named a new CEO: Satish Dhanasekaran will take over the post in May. Currently Keysight’s COO, he has been with the company since 2006 and previously led the Communications Solutions Group. Current president and CEO Ron Nersesian will be retiring but will continue as Executive Chairman of the Board. “Through the Board’s succession planning process, Satish’s market expertise, strategic insight, and high-performance track record made him the clear choice to lead Keysight,” said Nersesian.

EMA Design Automation, Cadence, and Rochester Institute of Technology teamed up to produce college-level PCB design courses for electrical engineers. The online and in-person course covers areas such as design and manufacturing fundamentals, CAD software familiarity, and incorporating design for manufacturing.