Week In Review: Design, Low Power

GDDR6 tapeout; analog/mixed-signal design management; pre-802.11ay IP.


Cadence taped out a complete GDDR6 memory IP solution consisting of PHY, controller and Verification IP on Samsung’s 7LPP process. The GDDR6 IP allows up to 16Gb/sec bandwidth per pin, or over 500Gb/sec peak bandwidth between the SoC and each GDDR6 memory die. It is targeted at very high-bandwidth applications including AI, cryptocurrency mining, graphics, ADAS and HPC.

ClioSoft debuted a SoC design management platform that integrates the company’s enterprise data management software into Mentor’s Tanner IC Design Tool Flow for analog/mixed-signal. The platform provides revision control, release and derivative management, Visual Design Diff and interfaces to commonly-used issue tracking systems. ClioSoft says it can be added into any design flow without having to modify existing design methodology.

Blu Wireless Technology uncorked a family of 802.11ay System IP that can be configured to reach throughputs ranging from 10Gbps to over 100Gbps and supports channel bonding and MIMO, as well as  dynamic feature TDMA scheduling, co-channel interference mitigation, accelerated packet aggregation, and 64QAM modulation. 802.11ay is set to be ratified in 2019; Blu Wireless says its IP supports many of the new proposed features.

DECA Technologies joined Mentor’s OSAT Alliance, making available to mutual customers a comprehensive tool flow and a new assembly design kit (ADK) for DECA’s M-Series advanced fan-out wafer-level package (FOWLP) process to be used with Mentor software.

RISC-V Summit: Dec. 3-6 in Santa Clara, CA. The first annual conference and exhibition dedicated to the RSIC-V ISA ecosystem. Training sessions, workshops, and presentations will be available, followed by a day for Foundation members.

Next year, the ESD Alliance will present ES Design West with a focus on IP, EDA, embedded software, design services, and infrastructure. Along with a dedicated conference track, there will be presentations and panels on the show floor. Co-located with SEMICON West, it will be held July 9-11 in San Francisco, CA.