The Rambus GDDR6 PHY IP Core

The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 6... » read more

GDDR6 PHYs: From The Data Center To Self-Driving Cars

The demand for ever-increasing bandwidth has resulted in a growing interest in GDDR across a number of market verticals, including data centers and the automotive sector. As an example of the former, deep learning applications require ever-increasing speed and bandwidth memory solutions in the data center. In deep learning and other emerging technologies, GDDR memory can help companies addre... » read more

The Week In Review: Design

Security Addressing the Meltdown and Spectre speculative execution vulnerabilities has not gone smoothly. Intel's firmware update caused unexpected behavior and a higher than expected number of reboots for its Haswell and Broadwell chips, leading the company to recommend users stop patching until an updated version of the patch is available. Microsoft's attempts to fix the issue left some W... » read more