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Week In Review: Design, Low Power

Navitas buys GeneSiC; higher bandwidth for UFS; RF design collaborations.

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The U.S. Commerce Department’s Bureau of Industry and Security (BIS) issued new export controls on EDA software aimed at designing gate-all-around FETs, which manufacturers plan to implement starting at 3nm (Samsung) and 2nm (Intel and TSMC). Specifically, the ruling controls export of software that is specially designed for implementing RTL to GDSII (or an equivalent standard) for GAA FET designs, or which is specially designed for optimization of power or timing rules in GAA FET designs, whether it is exported with a PDK or separately.

The ruling also bans export of gallium oxide (Ga2O3) and diamond substrates for ultra-wide bandgap semiconductors, which it says can be used to create chips with resiliency characteristics particularly desirable for military applications, as well as pressure gain combustion technology used in gas turbine engines, which can be used in aerospace and rockets. The new restrictions are part of the multinational Wassenaar Arrangement, which seeks to manage and track transfers of conventional arms and dual-use goods and technologies from participating nations.

Navitas Semiconductor acquired GeneSiC Semiconductor, a developer of silicon carbide (SiC) power devices, for approximately $100 million in cash, 24.9 million shares of Navitas stock, and possible earn-out payments of up to $25 million. The companies say GeneSiC’s technology will complement Navitas’ gallium nitride (GaN) power semiconductors, broadening market reach in electric vehicles, solar and energy storage, and industrial applications. GeneSiC was founded in 2004 and based in Dulles, Virginia, USA.

JEDEC updated the Universal Flash Storage (UFS) along with supporting standards. UFS 4.0 uses the M-PHY version 5.0 specification and the UniPro version 2.0 specification to double the UFS interface bandwidth and enable up to ~4.2 GB/s for read and write traffic. It also adds Multi-Circular Queue definition for more demanding storage I/O patterns and an advanced RMPB interface to allow increased bandwidth and protection for secure data. UFS targets computing and mobile systems such as smart phones and tablets where power consumption needs to be minimized.

Is it possible for any design to be bug-free? Check out this panel discussion from DAC, run by Semiconductor Engineering Technology Editor Brian Bailey:

Deals

Keysight’s PathWave RFIC Design (GoldenGate) is being integrated into Synopsys’ Custom Compiler design environment and PrimeSim circuit simulation solutions to enable designers to validate complex RF and millimeter wave design requirements for 5G/6G SoC and subsystem designs. “This integration enables customers to access Harmonic Balance and Envelope simulation capabilities, as well as Keysight’s Virtual Test Benches, to reliably compute error vector magnitude and adjacent channel power ratio early in the chip design and verification process,” said Niels Faché, vice president and general manager of Keysight’s PathWave Software Solutions.

Cadence provided an RF and mmWave flow for GlobalFoundries’ 22FDX platform. The full-flow RF solution was used to design and tape out a 28GHz 5G mmWave IC on the GF 22FDX platform and design an integrated antenna as a complete system-in-package solution. The mmWave IC design was simulated with the Cadence AWR Virtual System Simulator. The flows include system-level budget analysis, mmWave IC design, implementation, concurrent SiP co-design with integrated electromagnetic analysis, RF circuit simulation, reliability analysis, and physical verification.

MediaTek selected Keysight’s used 5G new radio (NR) device test solutions to validate the RF performance of 5G devices equipped with multiple input, multiple output (MIMO) and Massive MIMO antenna technologies in an over-the-air (OTA) laboratory-based test environment, providing the ability to simulate real-world radio channel conditions and automate validation of 5G devices.

Numbers and people

Synopsys reported fiscal Q3 financial results with revenue of $1.25 billion, up 18% compared to $1.06 billion in the same quarter last year. “We delivered excellent fiscal third quarter results, with broad-based strength, and are increasing our outlook for the year,” said Aart de Geus, chairman and CEO of Synopsys. “While our customers navigate through the ebbs and flows of the market, they are simultaneously investing heavily in more complex chips, more sophisticated systems, and more software. […] We expect to cross the $5 billion revenue mark in FY’22, with over 20% revenue growth, strong margin expansion and EPS growth, and more than $1.6 billion in operating cash flow.”

Keysight reported Q3 revenue of $1.38 billion, an increase of 10% compared to $1.25 billion in the same quarter last year. “We are again raising our full year outlook. We now expect to achieve revenue growth approaching 9% and earnings per share growth of approximately 20% for the full fiscal year,” said Satish Dhanasekaran, Keysight president and CEO.

Intel elected Lip-Bu Tan, executive chairman and former CEO of Cadence, to its board of directors. Also the chairman of Walden International and founding managing partner of Celesta Capital and Walden Catalyst Ventures, Tan will join the board’s M&A Committee.

Read more

Find more of the week’s news at Manufacturing, Test and Auto, Security, Pervasive Computing.

Check out the latest Low Power-High Performance newsletter to read about some of the new uses for AI in chips, a very cool technology, and why storing everything in the cloud isn’t the answer to archiving data. And in the latest Systems & Design newsletter, selecting an appropriate tool chain for custom processors, a fundamental shift in the economics of processing put attention on ASICs, and common themes at DAC.



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