Week In Review: Design, Low Power

1.84 PB of data from laser-powered chip; backside power delivery takes shape; TSMC certifies EDA tools; Renesas and Cadence earnings way up.


Tools and IP

Scandinavian researchers used a laser-powered chip to transmit about 1.84 petabytes of data over a fiber optic cable in one second. The scientists said the technology could lead to faster broadband speeds and reduce the amount of energy used to keep the internet running.

Imec said the semiconductor industry is likely to see increasing separation of power delivery and signal routing in coming years, lowering voltage and reducing metal routing congestion. All of the leading-edge foundries have announced plans for backside power delivery. Imec also said it is working toward lowering charge noise in silicon spin qubit devices.

New failure models are emerging as more complex IP blocks are combined. The industry is only beginning to identify the correct abstractions for these models. Read more here.

EDA leaders made a slew of announcements this week based on new technology from TSMC. Siemens announced that TSMC certified the Calibre nmPlatform tool for IC physical verification sign-off is fully certified for TSMC’s advanced N4P and N3E processes, and also certified the ​​Analog FastSPICE platform for N4P and N3E processes. Also this week, Siemens launched a cloud-native electrical design SaaS tool called Capital Electra X, and said its Teamcenter PLM product is now available on Google Cloud.

Cadence said its RFIC products support TSMC’s N16RF Design Reference Flow and process design kit. Its Integrity 3D-IC platform achieved certification for TSMC’s 3DFabric offerings. In addition, it developed a node-to-node design migration flow for custom/analog IC blocks, and said its digital and custom/analog design flows were certified for the latest TSMC N4P and N3E processes in support of the new Design Rule Manual and FINFLEX technology. Cadence also  announced that it joined the new Intel Foundry Services U.S. Military, Aerospace and Government Alliance to “support mutual customers with the domestic development and delivery of system-on-chip (SoC) designs.”

Synopsys, Ansys, and Keysight said their new millimeter wave radio frequency design flow is available for TSMC’s 16 nm finFET Compact technology. The design flow is aimed at addressing the performance and power demands of 5G/6G SoCs. Ansys also said its Redhawk-SC and Redhawk-SC Electrothermal multiphysics power integrity and 3D-IC thermal integrity products were certified for use with TSMC’s 3Dblox standard. Lastly, Ansys said a multi-year agreement with Murata builds on the companies’ existing relationship to allow Murata to leverage Ansys electronic system design tools to develop high-frequency devices and communication modules.

Synopsys announced that its digital and custom design flows were certified on TSMC N3E technology, and that the flows as well as the Found and Interface IP portfolios achieved multiple successful tapeouts. Furthermore, the company said its EDA and IP solutions for 2D/2.5D/3D multi-die systems are now available for TSMC’s most advanced N7, N5 and N3 process technologies.

It is technically possible to create a bug-free design, but doing so may not be worth the time and cost. Read more here.

Rambus released a new interface subsystem for high-performance data center and AI SoCs. The PCI Express 6.0 Interface Subsystem is comprised of PHY and controller IP. Scott Houghton, general manager of Interface IP at Rambus, said the “rapid advancement of AI/ML and data-intensive workloads is driving the continued evolution of data center architectures requiring ever higher levels of performance.”

Hyperscalers and automotive OEM’s are becoming fabless IDMs. The vertical integration trend is disrupting the industry’s cycle of customization and standardization. Read more here.

Financial Results

Renesas reported its third quarter financial results. The company earned 387.1 billion yen for the three months ending Sept. 30, the equivalent of about $2.65 billion. That’s an increase of 49.8% compared with the same period last year.

Cadence said it earned $903 million in the third quarter, an increase of 20.2% compared with the $751 million earned during the same quarter last year. “Generational industry trends are driving continued investment by semiconductor and system companies, and our broad, differentiated portfolio positions us extremely well to help our customers accelerate their next generation innovation,” said Anirudh Devgan, Cadence’s president and CEO.

Upcoming Events

Nov. 3, The Future of More Than Moore – Chiplets, Advanced Packaging, and More – SEMI Pacific Northwest Forum, online and in-person at Beaverton, OR

Nov. 10, Automotive Tech Day, Detroit, MI

Nov. 14-17, Supercomputing SC22, Dallas, TX

Nov. 15-18, Semicon Europa, Munich, Germany (co-located with electronica)

Nov. 21-22, CadenceLive Europe 2022, Munich, Germany

Nov. 29-30, Synopsys Memory Technology Symposium, virtual

Find more events here.

In Case You Missed It

Check out the new Systems & Design newsletter as well as the Low Power, High Performance newsletter for these highlights and more:

  • Raising IP integration up a level
  • Bespoke silicon rattles chip design ecosystem
  • How to make the right decisions about clock network architecture
  • Dealing with heat in near-memory compute architectures

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