Week In Review: Design, Low Power

QuickLogic buys sensor software startup; hybrid DSP/controller; GDDR6 IP.


QuickLogic acquired SensiML Corporation. Founded in 2017 as a spin-off from Intel, SensiML provides a Software-as-a-Service suite for developing pattern matching sensor algorithms optimized for ultra-low power consumption using machine learning. Details of the deal were not disclosed, though QuickLogic will fund it with shares of common stock.

CEVA debuted an all-purpose, hybrid DSP/controller architecture. CEVA-BX retains the low power requirements of DSP kernels and adds high-level programming and compact code size requirements of a large control code base. It features an 11-stage pipeline and 5-way VLIW micro-architecture, parallel processing with dual scalar compute engines, and load/store and program control that reaches a speed of 2 GHz at TSMC 7nm process node using common standard cells and memory compilers. The ISA supports SIMD as well as half, single and double precision floating point units.

CEVA also uncorked a neural network-based speech recognition technology for voice assistants. WhisPro provides always-listening multi-trigger phrase support with trigger phrase customization and works with both the company’s front-end voice processing software and DSP-based hardware and software. CEVA says the combination provides a recognition rate of more than 95%. It operates locally on an edge device, without the need for cloud back up.

Toshiba announced deep neural network (DNN) hardware IP for ADAS and autonomous driving which it says provides more accurate detection and identification of a wider range of objects than image recognition based on conventional pattern recognition and machine learning. It will be integrated with conventional image processing technology in the company’s upcoming Visconti5 image recognition processor.

Innosilicon produced silicon-proven commercial GDDR6 IP on Samsung’s 14LPP process. It supports two 16 bit channels and provides up to 16 Gbps per pin with a maximum bandwidth of up to 64 GB/s. It is fully compliant with the JEDEC JESD250 standard.

Innovium adopted Synopsys’ IC Validator tool for physical signoff of its 12.8 Tbps throughput TERALYNX switch. Innovium said it completed full-chip DRC and LVS signoff on TSMC’s 16nm FinFET process within one day.

Vayyar Imaging selected Cadence’s Tensilica Vision DSP for its advanced millimeter wave 3D imaging SoC capable of covering imaging and radar bands from 3GHz to 81GHz with 72 transmitters and 72 receivers in a single chip. Vayyar cited high performance, vast instruction set, small core area, low power demands, and performance/milliwatt.

Optek incorporated Cadence’s Tensilica HiFi 3 DSP in its latest OTK528X Bluetooth 5.0 dual-mode audio/voice SoC. Optek cited the software ecosystem as well as simplified development and workload reduction from using a single system software architecture for both controller and DSP.

EDA and IP revenue increased 6.7% worldwide in Q3 2018 to $2.44 billion, compared to $2.28 billion in the same period in 2017, according to the ESD Alliance. Each region saw growth, ranging from a four-quarters moving average of 11.8% in the Americas to 5.1% in Asia/Pacific. Much of the growth is being attributed to startup activity and the increasing number of companies jumping into the automotive market. Hiring growth continued as well, with tracked companies employing 42,162 professionals in Q3 2018, up 8% from Q3 2017 and 1.1% from last quarter.

DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs. Advanced registration rates close Jan. 28.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.

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