Week In Review: Design, Low Power

M&A
Ansys will acquire Helic, a provider of electromagnetic crosstalk analysis and signoff tools. Founded in 2000, Helic’s tools included pre- and post-LVS EM modeling, inductor synthesis and modeling, and analysis of crosstalk risk. The company’s technology will be integrated into a solution for on-chip, 3D integrated circuit and chip-package-system electromagnetics and noise analysis. The deal is expected to close in the first quarter of 2019; details were not disclosed.

Ansys will also acquire Granta Design, a provider of materials information technology. Founded in 1994 as a spin-out from the University of Cambridge, Granta provides tools to manage materials data and explore the impact of different materials on products as well as educational resources. Granta will continue to integrate with a range of PLM, CAD and CAE solutions. The deal is expected to close in the first quarter of 2019; details were not disclosed.

Tools & Standards
Aldec debuted the latest version of its HES Proto-AXI software package that serves as a Host-to-FPGA bridge in FPGA-based prototyping and HPC/High Frequency Trading applications. It now supports HES-XCVU9P-ZU7EV including a comprehensive collection of FPGA prototyping resources, and the HES Proto-AXI module now includes interrupt support and a Python API.

Synopsys uncorked the DesignWare ARC EM Software Development Platform for software development and debug of all ARC EM processor-based SoCs. It includes an FPGA-based hardware board with commonly used peripherals and interfaces such as USB, SD card, Bluetooth (BT4.0), WiFi (802.11abgn), 9D motion sensor digital microphone input, and ADCs. Additionally, online access to device drivers, examples, and a suite of free and open-source software is available through the embARC Open Software Platform.

The Multicore Association released an updated version of its Software/Hardware Interface for Multicore/Manycore (SHIM) processors and tools. SHIM 2.0 includes enhanced capabilities for modeling complex processor architectures including heterogeneous functional units, pipelining effects, and 32-bits vs. 64-bits, and single-instruction-multiple-data instructions (SIMD). It also improves modeling of power consumption, allowing the use of different voltages and frequencies associated with individual processor or clusters.

Deals
MorningCore Technology licensed Flex Logix’s EFLX4K eFPGA for TSMC 12nm FinFET Compact (12FFC) process. It will be used in a wireless communications application. MorningCore is also licensing additional seats of the EFLX Compiler so some of their customers can program the chip with eFPGA themselves.

NETINT Technologies licensed Arteris IP FlexNoC Interconnect for use in its PCIe 4.0 enterprise SSD storage system controllers with on-chip video processors. NETINT cited high bandwidth and data accuracy between the on-chip PCIe 4.0 interface and all internal subsystems as well as high bandwidth and low latency on-chip communications.

Deep learning on edge processor startup Hailo expanded its Series A funding round to $21 million. The round was led by Chinese venture capital firm Glory Ventures and will allow the company to expand its target markets into China and Hong Kong. Hailo is also launching an early evaluation period for select customers.

Events
DVCon 2019: Feb. 25-28 in San Jose, CA. This year’s keynote will argue why it’s important to have an integrated digitalization strategy. Other highlights include a tutorial covering new features in IEEE 1800.2-UVM, a workshop on functional coverage in SystemC, and panels on deep learning and the verification of open ISAs. Advanced registration rates close Jan. 28.

DATE 2019: Mar. 25-29 in Florence, Italy. The conference and exhibition will feature keynotes on heterogeneous computing in cloud and HPC as well as the limitations of modeling frameworks for intelligent systems. Sessions will highlight emerging design technologies, design and test of secure systems, embedded systems for deep learning, and more. Advanced registration closes Mar. 13.