Week In Review: Design, Low Power

Synopsys will acquire QTronic GmbH, a provider of simulation, test tools, and services for automotive software and systems development. Based in Germany, QTronic was founded in 2006 and makes a virtual ECU platform as well as a test automation solution with test case generator. Terms of the deal were not disclosed.

VeriSilicon uncorked VIP9000, a highly scalable and programmable processor for computer vision and artificial intelligence. Using the company’s latest VIP V8 NPU architecture, VIP9000 provides scalable compute capability ranging from 0.5TOPS to 100s of TOPS. It enables neural network inference with different data formats based on design choice (INT8, INT16, Float16, Bfloat16) and also supports hybrid quantization (mixing data formats between neural network operations) natively.

The CCIX Consortium released a public version of the CCIX Base Specification Revision 1.0a v1.0 for evaluation by non-consortium members. The CCIX specification is an interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors independent of ISA. This public release includes all of the Base Specification 1.0a chapters with the exception of the CCIX PHY chapter.

Adesto’s FT 6050 Smart Transceiver SoC was updated to natively support LON, LON/IP, BACnet/IP and BACnet MS/TP protocol stacks, allowing BACnet workstations and LON network manager and integrator tools to natively field-configure, provision and monitor controllers as either LON or BACnet devices, or both. It targets automation and control networks, particularly for smart buildings.

Analytical Graphics, Inc. (AGI) and ANSYS are teaming up to provide multiphysics simulations with multi-domain mission-level modeling for the early stages of a missile defense system for the U.S. military to counter high-speed, highly maneuverable hypersonic weapons.

Cadence’s analog/mixed-signal IC design flow was certified for UMC’s 28HPC+ process technology. The complete AMS flow, based on UMC’s Foundry Design Kit (FDK), includes an actual demonstration circuit with a highly automated circuit design, layout, signoff and verification flow. The 28HPC+ process utilizes a high-performance High-k/Metal Gate stack to support broad device options.

Faraday Technology debuted its 28Gbps programmable SerDes PHY IP for networking applications on UMC 28HPC process technology. The IP supports multiple interface standard protocols, such as OIF-CEI, JESD, PCIe Gen1-4, and Ethernet.

ANSYS reported second quarter 2019 financial results with revenue of $368.6 million, up 21% from the same quarter last year. On a GAAP basis, earnings per share were $1.28, up 19% from $1.08 per share in Q2 2018. Non-GAAP earnings per share for Q2 2019 were $1.61, also up 19% from $1.35 in the same quarter last year.

Events
Find upcoming semiconductor industry events here, including the the Hot Chips Conference (August 18-20) and the ARM Research Summit (Sept 15-18).