Week In Review: Design, Low Power

M&A
ANSYS will acquire Livermore Software Technology Corp. (LSTC), a provider of explicit dynamics and other advanced finite element analysis technology. Based in Livermore, CA, LSTC was founded in 1987 to commercialize the DYNA3D technology developed at the Lawrence Livermore National Laboratory. DYNA3D became the company’s premier product LS-DYNA, a general purpose nonlinear finite element program capable of simulating complex real world problems. LSTC counts the majority of tier one automotive suppliers among its customers, according to ANSYS, and has been a company partner for nearly 25 years. “I expect that the combination of [ANSYS] Workbench and LS-DYNA will expand our user base by at least an order of magnitude,” said LSTC founder and CEO John Hallquist. The deal is valued at $775 million, of which 60% of the consideration will be paid in cash and 40% will be paid through the issuance of ANSYS common stock. The transaction is expected to close in the fourth quarter of 2019.

HCL Technologies acquired Sankalp Semiconductor, an analog, digital, and mixed-signal SoC design services provider. Founded in 2005 and based in Hubli, Karnataka, India, Sankalp provides design services to companies in the automotive, consumer electronics, industrial IoT and medical electronics spaces and also offers a range of interface and IO IP. “Sankalp will complement our strong semiconductor offerings and help offer a wider range of services to our customers in the Analog & Mixed signal space” said GH Rao, President – Engineering and R&D Services, HCL Technologies. “Sankalp will operate as a 100% subsidiary of HCL.” Sankalp previously acquired the semiconductor division of KPIT Cummins in 2012 and Interra’s Memory & EDA business unit in 2016. Terms of the deal were not disclosed.

Rambus will pay $65 million in cash for the Silicon IP and Secure Protocols business of Verimatrix, formerly Inside Secure. Verimatrix’s embedded team will join Rambus. The acquisition is expected to close this year.

Tools & IP
Synopsys debuted its complete DesignWare Compute Express Link (CXL) IP solution consisting of controller, PHY, and verification IP. Built on Synopsys’ PCI Express 5.0 IP, the CXL IP is compliant with the CXL 1.1 specification and supports all three CXL protocols (CXL.io, CXL.cache, CXL.mem) and device types. The 512-bit CXL controller enables a x16 link for maximum bandwidth with extremely low latency, while the 32 GT/s PHY allows for more than 36 dB channel loss across PVT variations for long reach applications. The Verification IP for CXL verifies I/O, memory access, and coherency protocol features with built-in sequences, checks, and coverage for all link configurations up to 16 lanes and 32 GT/s data rates. The CXL IP targets AI, memory expansion, and high-end cloud computing SoCs.

Aldec updated its HES Proto-AXI software, adding support for the QEMU open source machine emulator and virtualizer as well as SystemC TLM version 2.0 to allow for the linking of design components, running on a HES board and connected with HES Proto AXI infrastructure, with the CPU sub-system running the Virtual Platform. Other enhancements increase the interoperability of HES Proto-AXI with third party tools as well as Xilinx Vivado and Microsoft Visual C++ support.

ANSYS uncorked ANSYS Autonomy, part of ANSYS 2019 R3, a set of tools for autonomous vehicle development and testing that includes advanced closed-loop scenario simulation, automated driving and control software development, functional safety analysis, and sensor, camera, lidar, and radar simulation. A recent deal with Edge Case Research added tools to evaluate the safety of AI-based perception software systems and reduce object detection defects in autonomous systems. Additionally, Autodesk’s automotive 3D visualization and virtual prototyping software has been connected with ANSYS’ physics-based lighting simulation solutions to add accurate lighting simulation to visualizations of vehicle interiors.

Arm will offer high-accuracy and high-integrity GNSS positioning solutions from Swift Navigation as an option on Arm-based platforms to developers of autonomous and connected vehicles. The GNSS positioning engine software is receiver-agnostic and works with a variety of automotive grade chipsets and inertial sensors for high-precision, lane-level localization.

Synopsys teamed up with Google and NetApp to enable Synopsys VCS simulation workloads on Google Cloud. In particular, the Preemptible VM feature in Google Cloud was noted to help reduce hardware cost as verification jobs scale to thousands of compute instances, while NetApp integration bridges on-premises and cloud infrastructures.

Standards
The MIPI Alliance made its nine debug and trace specifications publicly available for download. The aim is to give device developers a standard, layered set of interfaces and protocols to address debug requirements specific to mobile devices, providing an alternative to using dedicated debug and test equipment. Additionally, MIPI SPP v2.0 specification is now available and introduces MIPI TinySPP, which is optimized for use with low-bandwidth and potentially high-latency interfaces such as MIPI I3C, the high-performance, low-power interface for links between sensors and application processors.

JEDEC published document release 5 of the DDR4 Serial Presence Detect (SPD) Specification. Among the changes in the released SPD and label documents are support for the DDR4 NVDIMM-H, a proposed memory module based on a combination of DRAM and NAND Flash that provides NAND Flash accessed as a block oriented device.

Check out upcoming industry events and conferences: This month, the Arm Research Summit will be in Austin, TX on Sept. 15-18. The AI Hardware Summit is at the Computer History Museum in Mountain View, CA on Sept. 17-18 and the AI Summit will be Sept. 25-26 in San Francisco, CA. ORConf for open source design will be Sept. 27-29 in Bordeaux, France.