Week In Review: Design, Low Power

Tools & IP
Synopsys debuted its new DesignWare ARC EV7x Embedded Vision Processor family for machine learning and AI edge applications. The ARC EV7x Vision Processors integrate up to four enhanced vector processing units (VPUs) and an optional Deep Neural Network (DNN) accelerator with up to 14,080 MACs to deliver up to 35 TOPS performance in 16nm FinFET process technologies under typical conditions, 4X the performance of the ARC EV6x processors. In addition, the EV7x design combines clock and power gating technologies with architectural enhancements to reduce power consumption.

Cadence introduced the Celsius Thermal Solver, a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures that combines finite element analysis (FEA) for solid structures with computational fluid dynamics (CFD) for fluids. The solver provides transient as well as steady-state analysis and is based on a massively parallel architecture that the company says delivers up to 10X faster performance than legacy solutions without sacrificing accuracy.

CEVA unveiled NeuPro-S, its second-generation AI processor architecture for deep neural network inferencing at the edge with a focus on vision. CEVA also released CDNN-Invite API, a deep neural network compiler technology that supports heterogeneous co-processing of NeuPro-S cores together with custom neural network engines, in a unified neural network optimizing run-time firmware. The family includes NPS1000, NPS2000 and NPS4000, pre-configured processors with 1000, 2000 and 4000 8-bit MACs respectively per cycle. The NPS4000 offers the highest CNN performance per core with up to 12.5 TOPS @ 1.5GHz and is fully scalable to reach up to 100 TOPS.

Synopsys added new versions of its DesignWare ARC processor IP to support functional safety. The new ‘FS’ cores include the EM22FS, HS4xFS, and EV7xFS processors, which integrate hardware safety features such as redundant processors, error-correcting code (ECC), parity protection, safety monitors, and user-programmable windowed watchdog timers, to detect system errors and support ASIL B and ASIL D safety levels. Documentation including enhanced-safety manuals, FMEDA, and DFMEA reports are available. Additionally, the MetaWare and MetaWare EV compilers are ASIL D certified for development of ISO 26262-comliant software.

SmartDV uncorked IP for the Ethernet Time-Sensitive Networking (TSN) protocol. TSN requires that all devices be time-synchronized and deterministic to ensure data is not lost or delayed. The IP supports various Ethernet TSN standards and 10-, 100- and 1,000-megabit speeds, and is fully compliant with IEEE 802.1 specifications defining various components of time-sensitive networking.

Arm announced a new licensing model targeting academia. Building on its Flexible Access model, Arm Flexible Access for Research provides academic researchers access to a range of IP without fees or costs. The program includes the majority of processors within the Arm Cortex-A, -R and -M families, along with access to complete RTL subsystems and tools. It is expected to be available in early 2020. Additionally, Arm is launching an online community for researchers.

Synopsys released new versions of its Photonic Solutions portfolio, including RSoft for photonic device design, OptSim and ModeSYS for photonic system design, and OptSim Circuit and OptoDesigner for photonic integrated circuit design. The company also updated its LucidShape software for the design, simulation, and analysis of automotive exterior lighting products, adding freeform design and support for pixel light headlamps.

Numbers & Deals
EDA industry revenue increased 6.6% for Q2 2019 to $2,472.1 million, compared to $2,318.5 million in Q2 2018, according to the ESD Alliance Market Statistics Service. The four quarters moving average increased for all categories except services, and the Asia/Pacific region saw double digit growth. Hiring was up as well, with tracked companies employing 44,342 professionals in Q2 2019, an increase of 6.3% compared to the 41,706 employed in Q2 2018, and up 1.9% compared to Q1 2019.

Startup Celera Incorporated raised $3 million in a seed funding round to develop and commercialize a new AI-based software automation for the development of Analog/Mixed-Signal integrated circuits. Celera says it can speed development by 100X, enabling fully automated analog/mixed-signal design.

Infineon’s next-generation AURIX microcontrollers will integrate a new high-performance AI accelerator called Parallel Processing Unit (PPU) that will use Synopsys’ DesignWare ARC EV Processor IP. The PPU will accelerate AI algorithms such as Recurrent Neural Network (RNN), Multi-Layer Perceptron (MLP), Convolutional Neural Network (CNN), and Radial Basis Function (RBF).

Check out upcoming industry events and conferences: Coming up this month is the AI Summit, which will be Sept. 25-26 in San Francisco, CA. ORConf for open source design will be Sept. 27-29 in Bordeaux, France. Next month, Arm TechCon will take place Oct. 8-10 at the San Jose, CA Convention Center. Also on Oct. 10 is the PCB Systems Forum 2019 – Milan in Milan, Italy. Later in the month, the System-on-Chip Conference will be at the University of California, Irvine on Oct. 16-17, while the 13th IEEE/ACM International Symposium on Networks-on-Chip will be held Oct. 17-18 in New York, NY.