Week In Review: Design, Low Power

ANSYS will acquire Dynardo, a provider of simulation process integration and design optimization (PIDO) technology. Dynardo’s tools include algorithms for optimization, uncertainty quantification, robustness, scenario variation, sensitivity analysis, simulation workflow building and data mining. Based in Weimar, Germany, Dynardo was founded in 2001 and has been an ANSYS software partner; the acquisition will further integrate the workflow. Terms of the deal were not disclosed.

“We are thrilled to become part of the ANSYS family and look forward to enabling a broader set of customers to capitalize on the benefits of enterprise simulation management and to automate simulation and optimization activities across solution areas like autonomous systems, electrification, digital twins and simulation-driven data science,” said Johannes Will, managing director and co-founder of Dynardo.

Tools & IP
Arm unveiled two new machine learning processors as well as new graphics and display processors. The Ethos-N57 and Ethos-N37 NPUs aim to bring AI into mainstream devices. They are optimized for cost and battery life-sensitive designs, support Int8 and Int16 datatypes, and include data management techniques to minimize data movement. The Ethos-N57 is performance and power balanced and optimized for 2 TOP/s ML performance range, while the Ethos-N37 is designed for a small footprint and 1 TOP/s. Meanwhile, the Mali-G57 GPU has 1.3x better performance density and energy efficiency compared to the previous version as well as foveated rendering support for VR and better on-device ML performance. The Mali-D37 DPU, which offloads core display tasks from the GPU, focuses on area efficiency and is configurable to an area of less than 1mm2 on 16nm for Full HD and 2K resolutions.

Synopsys launched two new DSPs. The DesignWare ARC VPX5 DSP and VPX5FS DSP Processor IP are based on an extended ARCv2DSP instruction set and optimized for high-performance signal processing applications, such as RADAR/LiDAR, sensor fusion, and baseband communications processing. The ARC VPX5 DSP processors implement a configurable, energy-efficient very long instruction word (VLIW)/single instruction-multiple data (SIMD) architecture that combines scalar and vector execution units and offers safety monitors, lockstep capabilities, and other hardware safety features to support ASIL B and ASIL D.

Cadence uncorked Verification IP for the new NVM Express 1.4 (NVMe) protocol. It is integrated with VIP for PCIe 5.0 and includes a complete UVM SystemVerilog API for integration and SoC-level test creation. Included is a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with ready-to-run tests to ensure support for the specification.

Imagination debuted a new IEEE 802.11a/b/g/n 1X1 SISO Wi-Fi IP solution comprising of RF, baseband and MAC, supporting both 2.4GHz and 5GHz spectrum. The iEW220 is designed for low power applications in TSMC 40 and is supplied as a hard macro for the analog section and synthesizable RTL for the digital sections. Total size is less than 6mm2 and it is pre-certified to Wi-Fi Alliance IEEE 802.11n, WPA3, WMM-PS and PMF test plans.

Renesas expanded access to its portfolio of IP, including 7nm SRAM and TCAM as well as leading-edge standard Ethernet time-sensitive networking (TSN) IP. Renesas is also working on providing a system IP which includes PIM (processing in memory).

VeriSilicon uncorked its FD-SOI Design IP Platform, which comprises over 30 IPs based on GlobalFoundries’ 22FDX process. It includes low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs.

SiFive announced a new platform security architecture, SiFive Shield, to provide secure lifecycle management with secure key generation, storage, and provisioning. Compatible with the RISC-V ISA, it offers FIPS verified true random number generation, fault detectors and secure cryptographic engines.

Deals
Astera Labs, Synopsys, and Intel teamed up on a PCIe 5.0 system with 32 GT/s speeds for next-generation server workloads. The demonstration system features Intel’s PCIe 5.0 test chip, Synopsys’ DesignWare Controller and PHY IP for PCIe 5.0, and Astera Labs’ Smart Retimer SoC.

ASE Group adopted an ANSYS Customization Toolkit as part of its IC packaging and development process. ASE’s ANSYS ACT extension reduces human error by converting complex manual analyses into an automatic search process to identify critical reliability issues such as cracking and interface delamination, which it said reduced overall development time by 30%.

Numbers
Cadence reported third quarter 2019 financial results with revenue of $580 million, up 9% from the same quarter last year. On a GAAP basis, income per share was $0.36, up 2.9% from $0.35 per share for the same period in 2018; non-GAAP income per share was $0.54 in Q3 2019, up 10% from $0.49 in Q3 2018. “We are raising our outlook for revenue, operating margin, earnings and cash from operations for the year while we continue to invest in proliferation opportunities with market-shaping customers,” said John Wall, senior vice president and CFO.

Events
Check out upcoming industry events and conferences: DVCon Europe heads to Munich, Germany, on Oct. 30-31 with keynotes, tutorials, sessions, panels, and show floor. The 2019 Phil Kaufman Award will be presented to Mary Jane Irwin on Nov. 7, with a presentation and dinner beginning at 6:30 p.m. in San Jose, California. Returning to Europe, the ESD Alliance will host a program during SEMICON Europa in Munich, Germany, on November 13 featuring a series of presentations and a panel discussion highlighting how advances in electronic system design are enabling emerging and future applications.