Week In Review: Design, Low Power

Tools
Synopsys debuted the VC SpyGlass RTL Static Signoff platform featuring new noise reduction technology that uses machine learning to reduce noise by 10X without loss of quality of results. It also provides comprehensive CDC and RDC analysis to catch logic issues added during implementation, and is integrated with Synopsys’ automated debug system.

Ansys released RaptorH, a tool that combines Ansys HFSS and Ansys RaptorX into a single analysis solution to simulate electromagnetic phenomena on advanced nanometer silicon designs across multi-chip 3D-ICs, silicon interposers and advanced packaging. It targets 5G, 3D-IC, and RF IC design workflows with ways to overcome unwanted electromagnetic interference.

Pro Design launched the proFPGA XCVU37P FPGA module, a FPGA-based prototyping solution. Assembled with a Xilinx Virtex UltraScale+ XCVU37P FPGA including HBM, the module targets AI, deep learning, data center, image/video analysis and other bandwidth-intensive applications. In combination with high-end PCB material and high-speed connectors, the new FPGA module reaches a point-to-point speed of more than 1.4 Gbps single-ended over regular FPGA IOs and a performance of up to 25 Gbps over the multi-gigabit transceivers (GTY). It contains 8 GB HBM DRAM and offers an ASIC equivalent capacity up to 15 million gates.

IP
Cadence unveiled Verification IP for PHY designs, covering multiple protocols. Interfaces and protocols the VIP supports include PIPE 5.2 for PCIe 5.0, USB3 and USB4, DFI for LPDDR4, DDR5 and HBM2E, and MIPI D-PHY/C-PHY for CSI-2 2.0 and DSI 2.0. Capabilities include PHY-level timing checks, ability to drive protocol-aware and protocol-agnostic traffic for exhaustive testing, a built-in scoreboard for analyzing receive path, transmit path and loopback, and control over jitter, spread spectrum clock and bit error rate.

Synopsys announced silicon-proven HBM2E PHY IP operating at 3.2Gbps on TSMC’s N7 process and CoWoS advanced packaging technology. The HBM2E PHY provides an aggregated bandwidth of 409 gigabytes per second and was verified by integrating the test chip with the IP and HBM2E SDRAMs using 2.5D packaging.

UltraSoC uncorked CAN Sentinel, new IP that adds a hardware-based layer of security into the automotive CAN bus. Configurable with user-defined security rules, CAN Sentinel resides on the bus, monitoring transactions with a vehicle’s ECUs, identifying suspicious activity, preventing malicious messages and silencing attacks.

Mobiveil released its COMPEX Compute Express Link (CXL) IP. The COMPEX controller is designed to the CXL 1.1 specification and supports Host and Type 1, Type 2 and Type 3 device types. COMPEX also supports dual mode where it can be configured to operate either as a Host or any of the device types. It supports up to 16 Lanes on a flex bus interface and is compliant with PIPE 5.2 specification. It provides a simple packet-based interface to user logic that supports 128-bit, 256-bit and 512-bit datapath widths and provides a low-latency path for easy integration.

Arasan Chip Systems debuted eXpanded Serial Peripheral Interface (xSPI) IP, a universal NOR Flash Interface IP with support for Octal SPI, QSPI, Dual SPI and SPI Interfaces. It is compliant to the JEDEC JESD251 xSPI Specification V1.0. The xSPI IP also supports JESD216D Serial Flash Discoverable Parameters (SFDP).

Secure-IC and Menta collaborated to deliver Menta eFPGAs incorporating cryptographic IP (AES, RSA, etc) from Secure-IC with the aim of simplifying integration and enhancing programmability of cryptographic security features in complex SoCs.

Mentor teamed up with Imperas on a hardware Design Verification Flow for RISC-V processor implementations. The companies used the Google Cloud Open-Source RISC-V Instruction Stream Generator to develop and enhance the verification flow to compare the same corner case scenario for the functional behavior of the RTL-under-test, using the Questa platform environment against the golden reference model developed by Imperas.

Standards & People
Si2 launched a special interest group to focus on AI and ML opportunities and technology gaps in EDA. “AI and ML are changing semiconductor design and improving performance and time to market,” said Leigh Anne Clevenger, Si2 design automation data scientist.  “Based on member company interest, we expect the SIG to propose prototype projects to accelerate the development of standards in areas such as machine learning training, and data handling and sharing.”

Additionally, Si2’s oaScript Working Group published oaScript Version 4.0 to add design partitioning, multi-threaded parallel execution, and support enhancements available to OpenAccess in its most recent Data Model 6 upgrade.

Philipp A. Hartmann is the recipient of the 2020 Accellera Technical Excellence Award. Most recently Chair of the SystemC Language Working Group, Hartmann is being honored for his contributions to the advancement of the SystemC language standard, implementation and ecosystem. “Philipp has been an invaluable, active member of Accellera for many years, driving the evolution of the SystemC standard as well as being one of the most crucial contributors to the code development of the SystemC reference implementation,” stated Martin Barnasconi, Accellera Technical Committee Chair.

Events
Check out upcoming industry events and conferences: DVCon is Mar. 2-5 in San Jose, CA; key topics include formal verification, Portable Stimulus, IP security, intelligent system design, AI and ML-focused verification, 5G verification, UVM strategies, power-aware design and hybrid verification. DATE 2020 will be held Mar. 9-13 in Grenoble, France and will feature special days focused on embedded AI, silicon photonics, and a special initiative on autonomous systems design. On April 3 from 11:30 am – 1:30 pm in Milpitas, CA, the ESD Alliance will host investor Jim Hogan and Simon Butler of Methodics for a lunchtime discussion about bootstrapping a startup and successfully creating a new market segment.

Videos this week
Hybrid Prototyping looks at how to debug software and hardware before the hardware actually exists. Why PSS Is So Important examines the benefits of the Portable Stimulus Standard.