Week In Review: Design, Low Power

MaxLinear will acquire Intel’s Home Gateway Platform Division. MaxLinear, a provider of RF, analog, and mixed-signal ICs, will buy the Home Gateway Platform Division for an all-cash, asset transaction valued at $150 million. The division comprises Wi-Fi Access Points, Ethernet and Home Gateway SoC products deployed across operator and retail markets. The deal is expected to close in the third quarter of 2020.

Tools & IP
Synopsys unveiled new DesignWare ARC HS5x and HS6x processor IP families for high-performance embedded applications. The 32-bit ARC HS5x and 64-bit HS6x processors, available in single-core and multicore versions, are implementations of a new superscalar ARCv3 ISA and deliver up to 8750 DMIPS per core in 16-nm process technologies under typical conditions. The multicore versions of the new ARC HS processors include an interconnect fabric that links up to 12 cores and supports interfaces for up to 16 hardware accelerators, while maintaining coherency among the cores.  The processors can be configured for real-time operation or with an advanced memory management unit (MMU) that supports symmetric multiprocessing (SMP) Linux and other OSes.

Perceive Corporation emerged from stealth with its first product, the Ergo edge inference processor targeting consumer devices such as security cameras, smart appliances, and mobile phones. The company claims data-center level inference accuracy while retaining consumer security and low power usage. Perceive is a majority-owned subsidiary of Xperi Corporation.

CEVA rolled out a high performance sensor hub DSP architecture designed to handle the broad range of sensor processing and sensor fusion workloads for contextually-aware devices. The SensPro family can process and fuse data from multiple sensors including camera, Radar, LiDAR, Time-of-Flight, microphones and inertial measurement units. The configurable, self-contained architecture brings together scalar and parallel processing for floating point and integer data types, as well as deep learning training and inferencing.

Aldec updated its unified requirements lifecycle management EDA tool, Spec-TRACER, to support the exchange of data with IBM Requirements Engineering DOORS Next product, commonly used by system engineers. This new integration provides hardware teams immediate visibility of changes to the functional specification and aims to make meeting the traceability requirements of safety standard like DO-254 and ISO 26262 easier.

Flex Logix released benchmarking for its InferX X1 edge inference co-processor as well as its nnMAX architecture. The InferX X1 showed high throughput with low $ and watts. It has been optimized for edge applications with large models and large models at batch=1. The nnMAX architecture, upon which the InferX X1 is based, can be used for DSP acceleration for key functions as well as AI inference and for FIR filters is able to process up to 1 Gigasamples per second with hundreds and even thousands of “taps” or coefficients.

Deals
The Compute Express Link (CXL) Consortium and Gen-Z Consortium inked a plan of collaboration between the two organizations and promote interoperability between technologies. CXL and Gen-Z are both memory semantic protocols (read/write) that enable high speed connectivity to processors, accelerators and memory expansion. CXL focuses on enabling coherent node-level computing, whereas Gen-Z focuses on fabric connectivity at the rack and row level.

Faraday Technology Corporation expanded its SoC design services to use Synopsys prototyping solutions, including Platform Architect for SoC architecture design and optimization and HAPS FPGA-based prototyping for hardware and software co-design.

Events & Videos
Many conferences have now been cancelled, postposed, or moved online. Find out what’s happening with each at our events page. How about checking out a webinar instead? Plus, check out the latest videos to learn why different applications require very different process architectures in Stream Vs. Pool Data Processing and find ways to improve performance with more on-chip data storage in Last-Level Cache.