The Week In Review: June 7

DAC; Mentor adds cache-coherent interconnect verification; Synopsys adds field solvers for Samsung 14nm process; TSMC certifies Apache tools for 16nm; Atrenta rolls out new capabilities; Jasper teams with Duolog for SoC integration and verification.


By Ed Sperling
For all the hesitation about moving the Design Automation Conference to Austin, it turns out that Austin has a lot of hardware engineers. In fact they flooded into the conference, turning it into one of the most successful in recent years and setting new records in multiple areas. Even Texas Gov. Rick Perry showed up to see what all the fuss was about.

Mentor Graphics added cache-coherent interconnect verification into its existing verification and emulation platforms, a move that positions it to handle multi-core chips such as big.LITTLE implementations of ARM cores. The platforms will support ARM’s AMBA 5 CHI and AMBA 4 ACE specifications. Mentor also won a deal with Freescale for its test, physical verification, yield analysis and DFM tools.

Synopsys rolled out a design implementation solution for Samsung’s 14nm finFET process, including field-solver technology to model the parasitics of 3D transistors, high-performance models and support for physical implementation rules.

TSMC certified Apache Design’s power integrity and electromigration verification tools for 16nm finFETs for version 0.1 of the design reference manual and SPICE model. EM is one of the major concerns among EDA vendors for 3D transistors at the latest process nodes.

Atrenta uncorked version 5.1 of its verification and design exploration tools, including a new GUI with expanded space for debug, message grouping and filtering, as well as the ability to trace signal drivers across different hierarchies.

Jasper teamed up with Ireland’s Duolog Technologies to combine Duolog’s SoC integration tools with Jasper’s formal technology. The duo initially will deliver two flows, one for capture and verification of registration metadata, and the second to assemble, construct and verify SoC integration, including temporal and conditional connections and multiplexed I/O connections. Jasper also added power awareness to its formal verification tools, allowing RTL to be infused with power structure sequences, buffers to be inserted and then assertions to be extracted to verify the power sequencing is correct.

Arteris said its NoC IP was used in 60% of application processors and LTE modems developed in 2011 and 2012 for smart phones and tablets—the majority of mobile SoCs. Considering the growing use of third-party IP and time-to market pressures, there’s probably good reason why that market is seeing a surge.

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