TSMC updates reference flows using tools from all of the Big Three vendors.
By Ed Sperling
It’s reference flow update time as TSMC prepares to roll out both finFETs and stacked die capabilities, and advanced capabilities at 20nm. The foundry updated its reference flows to include tools and IP from all of the Big Three EDA companies.
It added Mentor Graphics’ place and route and DFM tools in its 16nm finFET reference flow, and added a slew of Mentor tools, including TSV parasitic extraction and thermal simulation, into its 3D-IC reference flow.
For the same flows, TSMC also added Cadence’s custom/analog tools for its 16nm finFETs, and Cadence’s custom/analog and signoff technologies for the 3D-IC reference flow. Cadence also rolled out a new version of its host controller IP for version 4.0 of the Secure Digital standard.
And for its 20SoC process technology, Synopsys unveiled a portfolio of IP including USB, DDR, PCIe and MIPI PHY.
ARM launched an MCU engineer accreditation program, or AAME, aimed at embedded software engineers. This appears to be the first of its kind for MCUs.
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