New tools not only need to check for errors but repair them as well.
The entire photomask design chain needs to be considered in the adoption of curvilinear photomasks. A broad look at the ecosystem impact was addressed in a previous video but a more in-depth look at the design chain of photomasks raises the next question – will MRC be harder and take more time? Aki Fujimura of D2S opens the nine-minute panel video with industry luminaries by providing a conceptual explanation of how curvilinear (curvy) MRC would work based on a paper presented by Ryan Pearman at Photomask Japan in 2019 as shown in figure 1.
Fig. 1: Conceptual explanation of curvilinear mask rule checking (MRC).
Ezequiel Russell from Micron Technology sees curvilinear masks adding complexity to MRC but that clever solutions are being discussed. He goes on to say that new tools not only need to check for errors but repair them as well. Fast algorithms for checks and repair will be key in order to make sure this new capability provided by curvilinear masks comes at the minimum cost possible in terms of processing time. Danping Peng from TSMC has an applied mathematics background, and based on that he believes there is an opportunity to simplify MRC for curvilinear masks. He provides some conceptual examples in the video and encourages electronic design automation (EDA) vendors to pursue a simplified approach. Noriaki Nakayamada from NuFlare Technology wraps up the video by discussing how their choice of data format in MBF 2.0 described in a previous blog could make curvilinear MRC easier. He calls for the industry to work together to converge on a solution.
You can watch the full 90-minute panel discussion for the eBeam Initiative’s virtual event at SPIE Advanced Lithography here.
Disaggregation and the wind-down of Moore’s Law have changed everything.
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Continued expansion in new and existing markets points to massive and sustained growth.
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Experts at the Table: Designing for context, and geopolitical impacts on a global supply chain.
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Nanosheets are likeliest option throughout this decade, with CFETs and other exotic structures possible after that.
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From low resistance vias to buried power rails, it takes multiple strategies to usher in 2nm chips.
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Disaggregation and the wind-down of Moore’s Law have changed everything.
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