When DDR DRAM Is Right For Automotive Systems

Most of the processors contained within automobiles are relatively small and with modest memory requirements that can be served by SRAM and non-volatile memory. The type of computing, image processing, and graphics displays that are possible with a more powerful CPU connected to DRAM have largely been restricted to the non-safety-critical infotainment system in the vehicle – until now. Advanced Driver Awareness Systems (ADAS) and self-driving vehicle systems demand powerful processors that require the memory capacity and bandwidth that is only possible with DRAM. Designers need to understand the benefits of using DRAM in safety critical automotive systems, as well as common concerns regarding error rates and meeting stringent automotive standards such as ISO 26262.

Benefits of DRAM in the automobile
DRAM is an enabling technology for these three automotive advances:

1. Displays: High definition displays generally require DRAM, and as displays like instrumentation consoles and heads-up displays will relay safety-critical information to the driver, then DRAM is needed in this safety-critical application.
2. ADAS systems that process camera and high-bandwidth sensor input: The cameras and other sensors that provide the input to the ADAS system generate a large amount of data which also requires further processing to remove noise, adjust for different lighting conditions, and to identify objects and obstacles. This kind of processing requires the bandwidth and capacity of DRAM.
3. Self-driving vehicles: Self-driving vehicles require processing of a number of high-bandwidth input sources and intense computation, making DRAM a necessity.

With these applications coming on-line, DRAM will be increasingly required for vehicles. DRAM will not replace SRAM, which will continue to be used for braking and engine management, but will provide new capabilities in ADAS and driver information.

Mitigating risk with automotive-grade LPDDR4 SDRAM
The core of a DRAM chip is an analog array of bit-cells that operate by storing a small amount of charge on a capacitor within each bit-cell – just a few tens of femtoFarads or just a few tens of thousands of electrons per bit, on a DRAM device with 4 or 8 billion bits per die. When introducing DRAM into a vehicle, we need to make some adaptations to the system to allow for the expected reliability under the operating conditions typically found in the vehicle.

One of the fundamental issues with DRAM bit-cells is that they leak charge and need to be periodically refreshed to avoid the loss of data in the memory. The rate of leakage is dependent on the temperature, leaking more at higher temperatures. Many automotive manufacturers have opted to put their camera-based ADAS modules on the windshield, where they benefit from being cleaned when the windshield is cleaned, but they also suffer from being in direct sunlight and potentially at a very high temperature when the vehicle has been parked in a hot climate in full sun. The operating temperature range for most automotive applications surpasses the normal DRAM operating range common to PC type applications which results in specially designed DRAMs targeted towards automotive applications.

The most common DRAM device for new ADAS designs is the LPDDR4 SDRAM. LPDDR4, originally designed for mobile devices offers a balance of capacity, speed and form factor that is attractive for automotive applications. As a result, LPDDR4 has been automotive qualified by DRAM manufacturers and is available in automotive temperature grades.

Addressing SEUs with in-line ECC
DRAM devices are also susceptible to soft errors due to Single Event Upsets (SEUs) – the effect of ionizing radiation on the DRAM device. In the case of an atomic decay within the DRAM device, or the effect of a neutrino or other cosmic particle strike on an atomic nucleus within the DRAM, a nearby bit-cell may lose its charge and again error correction should be employed to recover the lost data.

Even with careful physical interface design, at LPDDR4 data transmission speeds, there is a non-zero bit error rate, so the risk of data transmission errors must also be addressed.

There are a few possible ways to mitigate possible errors that may occur in DRAM devices to prevent the errors from propagating into the rest of the system. The DRAM manufacturer may attempt to create a bit-cell that is more temperature resistant, or the DRAM manufacturer may introduce error correction within the DRAM die to correct for the bit-cells which have lost their charge between refreshes. Even if error correction is present within the DRAM die, the SoC designer may also introduce error correction on the DRAM interface to correct errors in the DRAM.

In traditional DDR DRAM designs such as servers and networking chips, any error correction is usually transmitted side-band to the DRAM data. However, when using LPDDR4 devices, the arrangement of LPDDR4 into 16-bit channels, 2 channels per die, 2-4 dies per package, 4 channels per package means that it is highly impractical to implement sideband pins with which to transmit sideband Error Correcting Code (ECC) data. In that case, an in-line ECC scheme may be used, which transmits the ECC data on the same data pins as the data it protects (Figure 1).

Figure 1: Comparison of sideband vs in-line ECC

Meeting AEC-Q100 and ISO 26262 standards
When considering a SoC design to connect with off-chip DRAM, the SoC may be required to meet certain automotive reliability standards – typically AEC-Q100 and ISO 26262.

Hardened IP for implementing the DRAM interface can meet AEC-Q100 requirements with careful design and characterization. This includes both reliability and temperature components.

ISO 26262 has several requirements with components of process, design and certification among them. A core requirement is to have a defined design safety methodology and a safety manager tasked with implementing the processes. The DRAM interface IP requires extra circuits to periodically test the interface to make sure that the majority of errors that violate safety goals can be detected within a fraction of a second. Typically, a third-party certification is performed to rate the compliance of the design and assign an ASIL rating. The majority of automotive designs require at least ASIL B protection of the DRAM interface, while some designs may require ASIL D, the highest level of protection reserved for safety processors and their associated circuits.

Conclusion
DRAM devices are an enabling technology for advancements in automotive safety, features, and convenience. With careful design and stringent process, DRAM can be introduced into safety-critical areas of the automobile to provide high bandwidth and large capacity to enable the computing necessary for driver information systems, ADAS, and self-driving vehicles.

Synopsys provides a range of DDR interface IP including PHYs, Controllers, Verification IP, architecture design models, and prototyping systems. Ask your Synopsys representative about automotive-qualified IP for your next automotive design.