Why Is Semiconductor Schedule Predictability Boring?

Why is it not sexy to talk about the manageability of system-on-chip (SoC) projects? As an IP vendor, we are constantly bombarded with questions about how our technology can enhance performance, reduce latency, and lower power consumption. At the same time, reducing cost and time to market for the SoC design conflict with these requirements, even though they rank right up there among the top engineering manager worries in surveys.

Can we just sum up all these different aspects into one word? Manageability? Predictability? These are hard enough to say and even harder to execute. And the required technical metrics for any design project will vary by target market. For example, some projects in enterprise will focus more on performance, throughput and latency. On the other hand, mobile application processor and digital baseband SoCs will strive to achieve the greatest efficiency in order to prolong battery life, while still delivering a powerful user experience that depends a great deal on performance. But both of these projects have to get to market in a constrained time frame with just the right feature sets in order to capture market share.

As SoCs become more complex, and as design teams increasingly work on different aspects of the chip separately from one another, it is increasingly difficult to nail down the trifecta:

• Deliver the right features and performance;
• At the right time, and
• At the right price point.

To perform at this level and to take market share, the team that wins is the one that juggles all the tasks with almost perfect orchestration of all the variables. This is key in delivering the design that meets customer needs and executes on all of the key benchmarks.

Enterprise SSD Schedule Predictability
What if you were assigned to work on a next-generation enterprise SSD host controller SoC? Could your current team deliver the highest performance chip while adequately juggling myriad requirements? Many companies are entering this race to slug it out with incumbents because the massive shift from rotary hard-drive technology is presenting a golden opportunity for those who get to market first with an SoC that is off-the-charts in terms of innovation. Reducing latency and providing super-wide bandwidth are paramount for high performance. However, the enterprise SSD market is constrained by insane requirements for endurance and reliability, with continually shrinking market windows due to competition.

How do we manage all of these competing requirements? How can we focus on one aspect of the design without letting all the other equally important aspects fall behind in the process? And how can we rationally balance our design risks and increase schedule predictability?

One of the best ways to improve the predictability of an SoC design is by using the right on-chip interconnect. The interconnect interfaces with all the functional blocks on a chip and it is usually the last IP to be completed, so therefore, it can be configured to optimize the complete hardware system to meet all design metrics with maximum efficiency. Of course a network-on-chip (NoC) IP offers the most configurable interconnect available to designers today. Older interconnect technology based on crossbar-bus or mesh-grid hybrids has not evolved to keep up with the complexity of today’s enterprise requirements.

The SSD host controller mentioned above is not a hollow example, it is actually a case study of an Arteris FlexNoC user’s experience. One design team used the NoC interconnect to strike a balance between the needs for low latency, extremely high bandwidth, low power, and data protection while meeting strict schedule constraints. They were able to do so because all of the on-chip communications between the IP blocks was easily manageable through specification, simulation, synthesis, place-and-route, and verification.

Using the right interconnect IP enables a more predictable chip design process. For more detail on how NoC interconnect IP makes SoC project schedules more predictable, download the Arteris technical paper entitled, “Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-on-Chip Interconnect IP.”