Why Pinpoint Accuracy Is Important When Monitoring Conditions On Chip

A Q&A with Moortec CTO Oliver King.

Why is there an increasing requirement for monitoring on chip?

Since the beginning of the semiconductor industry, we have relied on a doubling of transistor count per unit area every 18 months as a way to increase performance and functionality of devices. Since 28nm, this has broken. As such, designers now need to find new ways to continue increasing performance.

Using the analogy of the internal combustion engine, for decades it was fine to have the fuel consumption and emissions that they had as the innovation was limited. Improvements to cars focused around adding features, adding things which made the car a nicer place to be. People bought new cars because they wanted the latest features. Then oil prices started going up, we became aware of the environmental impact, and with this innovation aimed at improving the efficiency of the engine. The result is quite astounding: the modern car engine delivers more power whilst consuming less fuel and emitting less harmful gasses.

The semiconductor industry is now in the position where it has to do the same. We can no longer rely on adding more transistors to make a better, faster chip. The customer still wants their new computer, phone, or tablet to be faster and have more storage than their old one.

One technique being deployed to provide the improvement is device optimization. Being aware of a device’s thermal and voltage environment and understanding where a given device is within the ever-increasing sphere of device variation allows the system architects and circuit designers to get more from a given piece of silicon. With the increase in the cost of advanced nodes, this is becoming even more important to ensure every last drop of performance is extracted from a die.

Is this just an issue for the advanced nodes?

In short, no. With the growth in the IoT market, we are starting to see an explosion in the number of wireless devices. A majority of these will be on older process nodes, however, the same performance gains can be found on these nodes. These devices will typically be battery powered and sensitive to power consumption. Because of this, there will be a drive to improve efficiency in these products rather than perhaps improving performance, but they are different names for essentially the same problem. By understanding where a given die is with respect to process, voltage, and temperature, a more optimum solution can be found. Whether that optimum solution is measured by performance or efficiency doesn’t matter.

Then we also have to consider automotive, which is a big growth area for the semiconductor industry as a whole. With the growth of the Advanced Driver Assistance Systems (ADAS) and Infotainment areas we are starting to see more advanced nodes like 28nm and FinFET being used. Ideally, some of these products would be on more advanced nodes, but some of those are not yet qualified for automotive. As a result, the available technologies are being squeezed by designers to get the extra level of performance. In addition, the environment in automotive is harsh. So when you look at all of these together it is clear there is definitely room for die optimization, as well as the requirement for basic monitoring purely for safety and reliability reasons.

How important is accurate monitoring?

Accurate PVT monitors are key to implementing die optimization. We all know the relationship between power consumption and supply voltage of CMOS logic. Being able to reduce the supply by even a few percent based on that particular die’s process point, also combined with the environmental conditions that allows, will result in power savings worth having. The same is true with performance, if a given clock speed can be met with a lower supply. But none of this is possible if the monitors are not accurate.

How critical has monitoring become?

PVT monitors are not anything new. They have been used in the industry for a long time, however, not generally in what I call mission critical roles. Once you start looking at optimization and potentially putting them into dynamic control systems, which is where we are now seeing customers use our latest generation of die monitors, then reliability and testability are absolutely critical.

Having features within the PVT monitors to ensure they can be tested easily in production is a minimum entry requirement, but in addition to that, being able to know the data from these monitors can be trusted is fundamental. As such, I believe having in-field fault detection and reporting built into the monitors is key. Let us consider the situation where a chip within a smartphone or tablet contains a temperature monitor which fails, and this failure effectively tells the system that the temperature is 0C when it is actually 50C, and because of this the system decides it can run with higher clock rates, pushing the die temperature up even further. The result could be very serious indeed. Because of this, robust operation of PVT monitors is becoming a primary concern.

Moortec’s latest generation of monitors feature exactly this level of robust operation and fault detection, complete with all the usual production testability which should be expected from such devices.

Where do you see the future of on chip monitoring?

On chip PVT monitoring is here now and it is here to stay. The costs of advanced node technologies are continuing to increase, and I think we are already starting to see a fragmentation, with the really advanced nodes becoming more niche for those devices which really need the performance. For those nodes, optimization will be part of the architecture to ensure the cost of those expensive technologies is minimized.

As the rest of the industry moves down to smaller nodes, they will look to differentiate their products from their competitor and good die optimization will play a part in that.

Oliver King is the Chief Technology Officer of Moortec Semiconductor. Before joining Moortec in 2012, Oliver was part of the analog design methodology team at Dialog Semiconductor and prior to that was a senior design engineer at Toumaz Technology. Oliver graduated from The University of Surrey in 2003 with a degree in Electrical and Electronic Engineering. Oliver has been leading the development of compelling in-chip monitoring solutions to address problems associated with ever-shrinking System-on-Chip (SoC) process geometries. An analog and mixed signal design engineer with over a decade of experience in low power design, Oliver is now heading up the expansion of Moortec’s IP portfolio into new products on advanced nodes.