Application-Specific Power Performance Optimizer Based On Chip Telemetry


As datacenter power consumption continues to pose cooling and cost challenges, and battery driven devices are expected to last longer between charges, the search for advanced power management mechanisms continues. A modern design must balance between maximizing performance, consuming the least amount of power, and guaranteeing no failures in field. The latter requires safety margins which tr... » read more

Mission Profile Analytics For The Automotive Industry


The automotive industry is undergoing a major transformation with the rise of electrification, connectivity, and autonomous driving capabilities fueling the need for a greater number of more advanced semiconductors. The associated regulatory expectations are also creating challenging safety and reliability requirements for automotive-grade silicon that need to be understood and managed over a w... » read more

proteanTecs On-Chip Monitoring And Deep Data Analytics System


High reliability applications in service-critical markets, such as autonomous driving and cloud computing, demand maximum performance and minimal power and cost. Reducing design margins while maintaining high reliability becomes imperative. State-of-the-art silicon processes offer mainly logic density improvements at limited speedup. Worst-case design analysis is not cost effective anymore. ... » read more

Chiplet Planning Kicks Into High Gear


Chiplets are beginning to impact chip design, even though they are not yet mainstream and no commercial marketplace exists for this kind of hardened IP. There are ongoing discussions about silicon lifecycle management, the best way to characterize and connect these devices, and how to deal with such issues as uneven aging and thermal mismatch. In addition, a big effort is underway to improve... » read more

Chip Monitoring For Max Performance And Security


In a semiconductor market dominated by SoCs for high-performance computing, AI, automotive and 5G, semiconductor companies face myriad challenges and device requirements. The specific challenges for any given SoC vary but can include issues around performance debug and security against hacking. Top of the list includes the need to ensure quality, enhance safety, optimize performance, and increa... » read more

Looking Inside Of Chips


Shai Cohen, co-founder and CEO of proteanTecs, sat down with Semiconductor Engineering to talk about how to boost reliability and add resiliency into chips and advanced packaging. What follows are excerpts of that conversation. SE: Several years ago, no one was thinking about on-chip monitoring. What's changed? Cohen: Today it is obvious that a solution is needed for optimizing performanc... » read more

Closing The Post-Silicon Timing Analysis Gap


Accurate static timing analysis is one of the most important steps in the development of advanced node semiconductor devices. Performance numbers are included in chip and system specifications from the earliest marketing requirements. The architects and designers carefully determine clock cycle times that can achieve the required performance using the chosen high-level architecture, micro-archi... » read more

Cybersecurity Through Hardware-Based Threat Detection And Mitigation


SoC design teams fill a mission-critical role in ensuring cyber-physical safety and security for electrical and electronic systems that are connected to the internet. The requirements and tools available to achieve this goal are ever-shifting, but we can be fairly sure that traditional software-only security measures are unlikely to be sufficient; a new class of hardware-level monitoring is als... » read more

Enabling Silicon Lifecycle Solutions


The concepts of product lifecycle management (PLM) should be familiar, although the semiconductor industry has yet to adopt a system for managing the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. Now, a combination of business and technical pressures is bringing PLM capabil... » read more

Better Optimization For Many-Core AI Chips


The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

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