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Better Optimization For Many-Core AI Chips


The rise of massively parallel computing has led to an explosion of silicon complexity, driven by the need to process data for artificial intelligence (AI) and machine learning (ML) applications. This complexity is seen in designs like the Cerebras Wafer Scale Engine (figure 1), a tiled manycore, multiple wafer die with a transistor count into the trillions and nearly a million compute cores. ... » read more

Building A More Secure SoC


SoC integrators know that a software-only chip security plan leaves devices open to attack. All that a hacker needs to do is find a way to replace key parts of the bootloader or the low-level firmware to compromise other software in the system used to support secure access. The most simple attacks come remotely over a network, and these can be patched with software upgrades. However, we see ... » read more

Will PAYGO Shake Up How We Pay for Chips?


System builders are used to buying integrated circuits on a simple transactional basis — the chip has a price, and that’s what you pay. But some application spaces may have a wide variety of capabilities that need hardware support, and each feature may not be used for every instance. Traditionally, one would design different chips for different feature mixes and price points. But a new p... » read more

Sensors Will Proliferate In SoCs


No one likes being put on the spot, and yet we all like a forecast…and as we all know, the only guarantee with a forecast is that it is wrong. Sports commentators have carved out a special niche for themselves with the ‘commentators curse:’ just as they extol the virtues of an individual or a team, the sporting gods prove them wrong in spectacular fashion! Governments are no better: econo... » read more

Scramble For The White Space


Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

The Quest To Make 5G Systems Reliable


Semiconductor Engineering sat down to discuss 5G reliability with Anthony Lord, director of RF product marketing at FormFactor; Noam Brousard, system vice president at proteanTecs; Andre van de Geijn, business development manager at yieldHUB; and David Hall, head of semiconductor marketing at National Instruments. What follows are excerpts of that conversation. SE: How do we measure the reli... » read more

A Historical Case For Precision


We take for granted today the staggering precision of modern technology. Cars, electronics, robots, and medical equipment all come off the factory floor composed of effortlessly interchangeable parts, but this was not always the case. In the late 18th century most things that required any kind of precision were made by hand, one notable example being the flintlock musket. You see, back then if ... » read more

Managing Worst Case Power Conditions


With each new technology node, especially FinFET, the dynamic conditions within a chip are changing and becoming more complex in terms of process speeds, thermal activity and supply variation. Dennard scaling brought about the ability for power to be scaled down with each successive node so that power per unit area stayed roughly constant. However, as highlighted by John Hennessy at last y... » read more

In-field In-Mission Reliability Monitoring Based On Deep Data


This paper describes a Deep Data approach to reliability monitoring in advanced electronics, based on degradation as a precursor for failure. By applying machine learning algorithms and analytics to data created by on-chip monitoring IPs (Agents), IC/system health and performance can be continuously monitored, at all stages of the product lifecycle. Realtime degradation analysis of critical par... » read more

No Two Chips Are Alike


As semiconductor processes continue to shrink it’s becoming increasingly challenging to manage the parameters of individual devices not only across the diameter of the wafer, but also across the length of a single chip, especially for a complex chip with a large area. Today’s standard approach to this problem is to assume the worst case and to create a sub-optimal design that accommodates t... » read more

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