Working With FinFETs

One of the key technology trends driving semi-conductor industry is the adoption of finFET processes. As opposed to a traditional planar transistor, the finFET has an elevated channel or “fin,” which the gate wraps around. Due to their structure, finFETs generate much lower leakage power and allow greater device density. Compared to planar transistors, finFET operate at a lower voltage and offer higher drive current. All of these lead to lower circuit delay, lower leakage and higher performance packed into a smaller area. This also means that finFETs offer reduced cost per unit performance.

In finFETs, with higher device density and drive current, peak currents are higher, too. As a result, on a large SoC the voltage drop, which is a function of the power grid resistance and the inductance (L) from the package, defined as equal to IR + Ldi/dt, becomes very critical. With planar transistors operating at 1V supply, a 100mV drop is only 10% of the supply. The same 100mV drop for a finFET with lower operating voltage is a much higher percentage of the supply voltage. This not only decreases the operating headroom and noise tolerance for the chip, it also increases the accuracy requirements for power noise analysis – increased accuracy in extraction of power grid, modeling of switching currents and accounting for the package/PCB impedance.

Along with the benefits finFETs offer, the increased current and power density and the reduced interconnect dimensions lead to higher temperatures and electromigration (EM) issues. Designers are much more limited in their device sizing and via/wire routing due to EM limits. The increased finFET temperatures lead to thermal effects like self-heating. An increase in temperature by 25° Celsius typically leads to a 3X to 5X degradation of the expected lifetime of devices and metal layers. To identify true EM weakness in a design, it is important to take into account the results of accurate thermal analysis. The higher the temperature, the lower is the mean time to failure. For advanced process nodes, this calls for close collaboration with a foundry and meeting their “sign-off” certification requirements with complex EM rules.

When designing a chip using advanced finFET process technology, it is important to follow a silicon proven methodology for mitigating power noise. Ansys RedHawk will enable:

• Robustness/connectivity checks. On an extracted layout, designers can perform grid weakness checks including missing vias, shorts, dangling instances/wires/vias and missing via connections on power straps. This will help in identifying the strength of the connection to the power and ground grid from cells or blocks. These early checks will help in reducing the time for iterations down the design flow.
• Static IR analysis. A static EM/IR analysis will identify the overall quality of power grid under average or DC conditions. Designers can use this check to ensure proper planning for power pads, power gates, as well as ensure proper hookup of IPs.
• Power and signal EM checks. This allows designers to validate data, clock nets & power nets to ensure they meet the RMS and peak EM limits. Both power and signal EM checks would help in identifying current density bottlenecks. Based on these checks, Designers can take action to size the metal segments to ensure conformance to reliability guidelines.
• Vectorless dynamic analysis. The best sign-off coverage for analyzing dynamic voltage drop is achieved using a multiple scenario vectorless analysis. Use of a statistical vectorless engine allows designers to determine the vulnerability of a design to simultaneously switching peak current events. Analyses in all modes of operation are critical for dynamic voltage drop noise coverage. For example, test or scan mode – even though it is typically at a lower frequency, lots of simultaneous switching occurs.
• Low-power analysis. This allows designers to run a variety of analyses including in-rush current analysis on designs with power gates to make sure inrush current does not exceed peak current and also coupling noise analysis between a gated and an always-on domain to identify hotspots.
• ESD analysis. With each new process node shrink, and the number of IPs used in a design growing, the occurrences of ESD interconnect failures increase, requiring layout-based resistance and current density checks to determine proper clamps and their placement. Proper clamp placement is critical to provide discharge paths during ESD events.
• Chip-package analysis (CPA). Increased noise sensitivity of finFETs creates the requirement for accurate noise analysis. This calls for modeling and including a per-bump package model of a package in the dynamic voltage drop (DVD) analysis of the chip used. RedHawk’s CPA capability is a co-analysis platform allowing a designer to use a fully distributed parasitic power and ground networks of a package with the chip layout. Designers can analyze and determine true grid weaknesses that are a function of the combined package and die power ground networks and identify the root cause of a hotspot.

Figure 1. Per Bump Analysis – Lumped Vs Distributed

• Thermal analysis, including self-heating. FinFET transistors trap heat generated by dynamic and leakage power consumption. The dissipation of that heat is restricted by the oxide layers isolating the fins and in-turn creating a self-heat phenomenon. Addressing this requires close collaboration with foundry data, and RedHawk is built-up to address this effectively. The increase in temperature can lead to higher EM related failures. Redhawk enables modelling localized thermal effects for FinFETs, as well as thermal-aware EM checking to ensure product reliability.

Figure 2. Self-heat Analysis

• Distributed machine processing (DMP) analysis. Many factors including the combination of process advancements, greater integration of design components, increased impact of thermal effects on design performance and reliability have resulted in the need for higher simulation capacity and turnaround time without compromising on accuracy. A variety of capabilities such as smart caching, multi-CPU processing, hierarchical modeling and DMP are offered to help a designer achieve the best throughput with power integrity and reliability analysis. Figure 3. shows some typical runtime improvements seen for a variety of customers

Figure 3. Sign-off Accuracy with Distributed Performance

Designing a complex SoC using advanced finFET-based technologies for first pass silicon success requires proven tools and methodology. ANSYS’ power integrity and reliability solutions with their long-standing sign-off certification from foundries is a testament to not only their accuracy, but also to the 1000’s of designs successfully implemented in silicon.

Additionally capabilities such as thermal, EM, ESD, CPA analyses offer the required coverage against the complex power integrity and reliability issues. Finally, DMP capability allows greater capacity and faster performance, enabling scalability and faster time to market – achieving better power integrity and reliability.

Register for this webinar on achieving power noise closure for advanced networking SoCs.