Yield Ramp Challenges Increase

As semiconductor manufacturing moves down to smaller process nodes, there’s no doubt that it is increasingly difficult to ramp both test and manufacturing yields.

One reason for this is simply scale. Smaller nodes translate into more steps and greater complexity in the manufacturing process, with attendant process variations.

“Smaller process nodes increase the amount of embedded memory and logic that can be packaged on a chip, which makes it more likely to fail,” according to Bassilios Petrakis, director of product marketing for test products at Cadence. “Advanced nodes inherently pose potential design challenges – higher layout density with more physical layers, interconnect vias, wiring congestion – and, of course, added test challenges – requirements for more advanced fault models and memory test algorithms, power considerations during manufacturing test, and the ever-increasing test data volumes that increase testing time and costs,”

In addition, for the first time there is a fundamental change to the structure of the transistor resulting in new defect mechanisms with major impact on the SOC design and manufacturing, pointed out Hem Hingarh, VP Engineering at Synapse Design.

“In particular, FinFET critical dimensions are for the first time significantly smaller than the underlying node dimensions, leading to increase in number and complexity of layout and circuit-sensitive defects. Also means variability from design to design, makes yield a continuing challenge even as the process matures. New test structures and technology bring-up methodologies are necessary to understand process induced variation, Layout and circuit design need to be optimized to mitigate the process impact,” he said.

Fundamentally, there are two kinds of defects that kill the yields: random and systematic.

Engineering teams get a grip on random defects by making the processes as clean as possible.

“All of the Class 1 fabs spend a lot of energy and money in making sure that random defectivity doesn’t get in,” said Anjaneya Thakar, product marketing senior staff for the Silicon Engineering Group at Synopsys. “Even having done that, just by the very nature that there is chaos in everything we do, either technically or in nature. There are problems with equipment, there are problems with interfaces and you could still have random defects that creep in.”

Over time, however, random defects are having less impact on the overall yield of a product with more yield problems traced to systematic defects. “The first wave of systematic problems was what gave impetus to all the resolution enhancement and proximity correction techniques. What that allowed us to do was solve some of the systematic problems that creep in because of issues. As geometries get smaller and smaller, these lithography issues which we could have ignored in the past are now dominant and we need to compensate for the lithography problems to make sure that we get yield,” Thakar said noted.

A 193nm light source is still used for the 20nm/14nm nodes, which means very thin lines are being painted with a very broad brush, and while this is a major source of yield concern, there are a number of techniques to resolve the issues associated with it. Still, the problems stem from the fact that the wavelength of light being used is much larger than the devices being manufactured. This is one of the reasons systematic defects are more prevalent than random defects.

Layered on top of this are the systematic problems that come in because of design issues. “For example, there could be timing issues because of the way two signals are laid out on a piece of silicon,” he explained. “There could be parasitic line capacitance and resistive issues that we could have ignored in the past but are becoming critical. Or things that are incorporated in the silicon because of the way we are used to doing our designs is a new source of yield issues when we get into manufacturing. For this reason, upstream from manufacturing we do ATPG and we do scan-chain insertion and we do scan diagnosis to figure out which devices on a particular piece of silicon are failing.”

This currently is being extended into the realm of statistical data processing, so if there is a timing issue or if there is a failing via issue on a particular chip, looking at that problem in the context of hundreds of thousands of dies and wafers will provide a better understanding of whether it’s just random or whether it is a systematic problem because of the way the initial chip was designed.

Next step: true yield analysis
Petrakis asserted that the only way to ramp yield is to be able to recognize and correct process-related defects. “As we get to smaller geometries, we may be seeing a higher incidence of random defects in addition to normal process variation. You cannot fix random defects by honing your process. As the percentage of random defects increases, so does the challenge of identifying systematic defects through traditional volume diagnostics. Identifying yield-limiters will require data collection for more failing devices and likely more data per device. More sophisticated analysis engines will be required to mine various types of data – correlation, statistical analysis, and pattern recognition and trend identification.”

The pain gets greater the lower in nodes one goes. “At 10 and 7nm, it will be absolutely necessary to understand the systematic defects, and which are non-random and systematic in nature and that are affecting yield because as you get to each new node the ramp becomes more and more difficult…the ability to early on in the development process of the node be able to understand the defect mechanisms that are arising and diagnose and identify those that are systematic and feed that back to the design side of things is going to become critical,” explained Steve Pateras, product marketing director for test at Mentor Graphics.

“Tying test to not only detecting these new defect mechanisms but diagnosing them and feeding that back to the physical design tools is something we are seeing becoming of interest and something we expect to become a critical requirement at 10 and 7nm and having that link between test and diagnosis and physical design,” he said.

Thakar agreed, adding that for these design or fab teams to confirm a problem actually is a problem, they have to collect a lot of data. “Volume of data is critical to make any statistical processing result meaningful. You cannot just take one wafer or one lot and say you have a systematic problem. You have to look through a large number of die and wafers to arrive at a source of systematic problems.”

Further, the ability to analyze that data is critical, he said. “How do you overlay fab monitoring data? When a wafer is going through a fab, there is a lot of data collected on the devices being manufactured. For example, there is a measurement of a width of a line at a specific place on a die. You keep doing that measurement for every wafer that goes through. Those are the inspection machines and metrology machines. How do you collect that data, then correlate it to a particular design attribute that says, ‘After looking at 100,000 die, I know that this particular cell has a marginality because it’s always failing for this particular measurement?’ The ability to collect that vast amount of data, overlaid with different sources of data — it could be timing, it could be layout, it could be defect data from the fab — and coming to a conclusion that says, ‘For this reason I believe the problem is with this particular standard cell or this particular flip flop.’ That whole data collection, analysis and narrowing down on very deterministic problem areas is something that’s still in the development stage.”

The optimal scenario is one that protects IP for both the foundry and the fabless companies. “Even while protecting their own intellectual property they could actually bring the data together,” Thakar said. “A fabless company could say, ‘Here’s my layout information.’ The fab says, ‘Here’s my defect data collection information.’ Let’s overlay these things on top of each other to see if there is any commonality. Today they don’t do it because the fabless companies believe any information with the fabs could get spread around, and vice versa. They could do it, but they don’t do it.”

Fortunately, there is some collaborative engineering happening because the problem is becoming so difficult to drill down into. As of now, it is still a top-heavy scenario between the largest fabless companies that have enough clout to deal with the foundries. Over time, this will include even the smaller, trailing edge foundries, he said.