Zeno Semi Expands On-Chip Memory

Shrinking SRAM expands on-chip memory with standard CMOS, FinFET.


San Jose, Calif.-based startup Zeno Semiconductor is testing modifications and a smaller process node for the single-transistor 28nm SRAM chip it introduced in 2016, which could boost space for on-chip CPU memory by more than 2.5X, according to the co-founder and CEO of the company, Yuniarto Widjaja.

The Zeno-1 transistor is built on standard CMOS processes, has a bi-stable bipolar transistor built into its structure, which includes an N-well buried under a floating P-well on top of a P substrate.

The memory bitcell is genuinely static; it does not require a capacitor or other mechanism to maintain or refresh charge during operation, a capability it creates using the intrinsic bipolar transistor that are intrinsic to both CMOS and FinFET.

Because it uses one transistor rather than six, it is dramatically smaller than comparable unite, Widjaja said, which gives CPU makers the chance to expand on-chip memory without expanding the size of the die.

“If you look at processors from companies like Intel, a lot of the space on the chip is taken up by embedded memory; they are running out of space on the die,” Widjaja said.

Deep learning and other memory intensive applications need more on-chip memory to perform well, which is why chips designed for those applications have unusual amounts of memory space.

Research says SRAM based on exotic materials could eventually provide the ability to scale, but the materials themselves limit new types of memory to roles in which SRAM can be used as a standalone resource, rather than being built-in, as is the current rule.

Zeno’s chip takes up 25% the space of SRAM built to the same process and is small enough at 0.025 sq microns that it is just 37% of the area of a six-transistor cell built on Samsung’s 10nm process, Widjaja said.

Designing the chip to use standard CMOS processes, using the  buried n-well implant under the memory array, allows it to use the same libraries, circuits and IP as any standard CMOS SRAM.

The Bi-SRAM memory schematic cross-section. Source: Zeno Semiconductor

The single-transistor version performs comparably to SRAM for standard applications; for HPC and other resource-intensive applications, the company makes a two-transistor version, according to Widjaja, who was originally considering the IoT as a major target market because of the size reduction in this approach. But the computing power is high enough for the 1-transistor version to aim both at more standard IT and datacenter-category computing devices.

The 2015 paper describing the chip for the first time confirmed that it could scale to 7nm process FinFET. The second version, which will be available to partners next year, will be built on a smaller process than the 28-nm original, Widjaja said, but could not confirm which one.

The same architecture can be used for logic circuits with a 4x gain in power/performance compared to standard versions.

Zeno has been granted or applied for a large number of patents, and plans to focus on selling or licensing its IP, according to Widjaja. The company has applied for or been granted more than 50 patents.

Source: Zeno Semiconductor

The company offers a royalty plan that emphasizes the savings in die area, Widjaja said.

“We make the customer’s die size smaller—by 25%, say. Die cost is proportional to size; the customer saves 25% of the cost, so the royalty is a small percentage of the amount they save,” Widjaja said.

“We don’t add to their cost. Customers save money using our chip and we get paid on that basis.”

The second version of the chip should be available for licensing as IP sometime during 2019, he said.

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