Facebook, Alibaba, Google, Apple and Samsung are all designing their own chips. So are Cisco and Huawei. So what exactly does this mean for big chipmakers and the semiconductor ecosystem? While your first impulse might be to draw a straight line between Qualcomm's decision to cut 1,500 jobs and reports about giant systems companies developing chips in-house, it's not clear there is any corre... » read more

Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA. https://youtu.be/0N1PDYyq0dY » read more

The merger of two standards organizations typically falls well below the radar of most engineers, but folding the ESD Alliance (formerly known as the EDA Consortium) into SEMI is a different kind of deal. Ever since the introduction of finFETs and multiple patterning, EDA tools have become an integral part of the development of new manufacturing processes. Without those tools, there is no po... » read more

Variation, edge placement error, and a variety of other issues at new process geometries are forcing chipmakers and EDA vendors to confront a growing volume of increasingly complex, and sometimes interconnected design rules to ensure chips are manufacturable. The number of rules has increased to the point where it's impossible to manually keep track of all of them, and that has led to new pr... » read more

SEMI unveiled plans today to merge with the ESD Alliance, the chip industry's top EDA tools group, following three similar moves by SEMI in other slices of the semiconductor supply chain. The consolidation among industry groups began several years ago, but it has accelerated recently with the rollup under SEMI's leadership of the FlexTech Alliance, the MEMS & Sensors Industry Group and the F... » read more

Benjamin Prautsch, Fraunhofer EAS' group manager for advanced mixed-signal automation, talks about how to simplify and speed up analog IP development, its role in IoT and IIoT/Industry 4.0, and why this is becoming so important for advanced packaging and advanced process nodes. https://youtu.be/6ISL1A7Wy_I » read more

AI, machine learning and autonomous vehicles will require massive improvements in performance, at the same power consumption level (or better), over today's chips. But it's obvious that the usual approach of shrinking features to improve power/performance isn't going to be sufficient. Scaling will certainly help, particularly on the logic side. More transistors are needed to process a huge i... » read more

ANSYS Chief Technologist João Geada talks about electrical overstress and circuit aging and how what it means for automotive electronics. https://youtu.be/4bjdr0uvWG4 » read more

Anand Raman, director of technical marketing at Helic, explains what's needed to improve confidence in designs at the most advanced process nodes. https://youtu.be/2O2pbMJSta4 » read more

The number of advanced packaging options continues to rise. The choices now include different materials for interposers, at least a half-dozen fan-outs, not to mention hybrid fan-out/3D stacking, system-in-package, flip-chip and die-to-die bridges. There are several reasons for all of this activity. First, advanced packaging offers big improvements in performance and power that cannot be ac... » read more