The Week In Review: Design

Synopsys acquires GSS in TCAD move; heterogeneous cache coherent interconnects; portable sequence generator; ESDA board.


Mergers & Acquisitions

Synopsys made a couple of announcements this week related to its TCAD business. First, they acquired Gold Standard Simulations, which clearly became a major factor in the release of a pre-wafer simulation solution to help semiconductor manufacturers reduce process node development time. The new solution aims to provide a comprehensive process, transistor and circuit simulation flow for evaluation of various transistor and process options using a design technology co-optimization methodology that starts in the pre-wafer research phase. Synopsys sees that the introduction of finFET in logic and 3D-NAND in memory implies that the complexity of new process nodes has increased significantly. They believe that this complexity will accelerate as future process nodes will need to evaluate and select among a larger number of processes, device architectures and materials. Synopsys also acquired Simpleware, which makes tools for turning 3D images into models that can be used in simulation.

Tools & IP

Moving from tiny devices to system-level issues, Synopsys announced a cache coherent subsystem verification solution for Arteris’ recently announced distributed heterogeneous cache coherent interconnect, Ncore. The Synopsys Network-on-Chip (NoC) subsystem verification solution generates UVM testbench logic that integrates with Ncore testbenches, for connectivity of new subsystem level tests, monitors, coverage and performance tests, and analysis. Additionally, Arteris utilized ARM’s Cycle Models to simulate ARM’s IP and verify compliance with the AMBA ACE protocol. NXP licensed Ncore, where it will be used in heterogeneous cache coherent SoCs for next generation automotive MCUs and processors.

Agnisys unveiled a portable sequence generator that can be used from early design and verification to post-silicon validation. Sequences are a set of steps to achieve certain functionality that involves writing or reading specific bit fields of the registers or memory in a SoC or IP block. Once defined, the tool will convert that into a portable sequence library for a variety of domains including the language to be chosen by the Accellera Portable Stimulus Working Group (PSWG). Agnisys also teamed up with Breker to integrate it with their family of products.


The ESD Alliance (formerly EDAC) held board elections this month. Seven previous members were re-elected to their seats. Additionally, Lucio Lanza, managing director of Lanza techVentures, was appointed by the ESD Alliance board in April and Amit Gupta, president of Solido Design Automation, was elected to fill the remaining board seat. The board will elect its new chair June 2.


Silicon Labs selected Mentor Graphics’ Analog FastSPICE platform for circuit verification and device noise analysis of its pre-layout and post-layout analog circuits, including PLLs, data converters, wired and wireless transceivers, and other specialized high performance analog and RF circuits.