August 2010

Experts At The Table: The Trouble With Corners

By Ed Sperling Low-Power Engineering sat down to discuss corners with PV Srinivas, senior director of engineering at Mentor Graphics; Dipesh Patel, vice president of engineering for physical IP at ARM; Lisa Minwell, director of technical marketing at Virage Logic; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversation. LPE: How does software affect ... » read more

Best Practices In Team Building

By Ed Sperling Putting analog and digital engineers in the same room used to elicit strange looks and under-the-breath comments, but most companies have gotten beyond that stage. Now the question is how to pair them up effectively, get them all on the same team—sometimes even with software engineers thrown into the mix—while still getting a product out the door on time. This is easier s... » read more

What’s Next After DRAM?

By Pallab Chatterjee At the most recent Denali Memcon, there was a panel discussion and debate about the future of DRAM and possible successor technologies. The discussion was moderated by Cadence’s Steve Leibson and featured Bob Merritt of Convergent Semiconductor, Barry Hoberman of Crocus, Ed Doller of Micron and Marc Greenberg of Denali/Cadence. The topic of the discuss was based on t... » read more

The Growing Software Challenge: From Stacks To SMP

By Ann Steffora Mutschler Building a system now includes software, but defining the software stack is a mounting challenge for engineers. What used to be almost exclusively drivers now includes RTOSes and OSes, executable files, middleware, firmware, IP, embedded software and applications. With millions of different embedded products, all with different sets of software, it comes down to pr... » read more

Extending Moore’s Law

By Ann Steffora Mutschler For Moore’s Law to perpetuate, the materials used in semiconductor manufacturing must do their part to allow the scaling of devices to occur. Some of the latest include a carbonless film deposition technology for 20nm transistors and smaller, a plastic memory device and a material compound of silicon, copper, nickel and iron that researchers believe could lower manu... » read more

The Shape Of Things To Come

By David Lammers Tall or thin? That is the question facing semiconductor companies, now reaching an “intense” phase in development of the vertical finFET and planar ETSOI (extra thin silicon on insulator) transistors for the 22/20nm and 15/14nm technology generations. “This is a conservative industry,” said Raj Jammy, vice president of materials and emerging technologies at Sematech... » read more

Betting On 3D

The continuation of Moore’s Law appears less in doubt than ever. Companies such as Intel, ST, AMD (via GlobalFoundries) and IBM are testing FinFETS and ETSOI and work is being done on the back end to ensure that these new structures can be manufactured with sufficient yield. What’s changed, though, is the resistance by other companies to the progression of Moore’s Law. There is no long... » read more

Don’t Leave Money On The Table

By Jack Harding The vast majority of private fabless semiconductor companies are venture funded and, rationally, anticipate an exit through acquisition. The statistics around achieving an exit via an IPO are daunting, at best. But, as we have all read, the valuations are much lower than they once were. One of the reasons is the recent valuations of the acquirers are lower. But there is ano... » read more

It’s Late Q3 – Do You Know Where Your Chip Is?

By Mike Gianfagna Design complexity is increasing. We all get that. But there are other forces at play that may be more significant. Supply chain complexity is also increasing. Outsourcing and off-shoring continue to rise. There exists a general tendency to surrender the fate of your chip to more people. Overlay this situation with the simple fact that in more and more cases the chip defines t... » read more

RTL Fault Coverage Estimation

This paper describes a method for estimating fault coverage from register transfer level (RTL) descriptions of complex circuits. The method does not require automatic test pattern generation (ATPG) or the use of fault simulation and therefore offers the advantage of very rapid turnaround with no additional user effort. An important benefit is the means for a user to quickly determine the change... » read more

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