December 2010 - Semiconductor Engineering

Moore’s Law Will Never End
By Ed Sperling - 17 Dec, 2010 - Comments: 0

Moore’s Law has been many things to many people. It has been a statement of physical limits and an economic formula. It has been the cause of overheating and complex power solutions, and it has been a competitive weapon among companies looking to boost performance and cut costs. It also has been revised on more than one occasion as the time frame in which the number of transistors doubles ... » read more

Experts At The Table: IP Integration Hurdles
By Ed Sperling - 17 Dec, 2010 - Comments: 0

By Ed Sperling Low-Power Engineering sat down to discuss IP integration issues with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at eSilicon; Mike Gianfagna, vice president of marketing at Atrenta; and Jim McCanny, CEO of Altos Design Automation. What follows are excerpts of that conversati... » read more

Supply Chain Adjusts To Design At The System Level
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Ann Steffora Mutschler System-level design is impacting the supply chain at many levels. Software suppliers, IP providers, semiconductor companies, system integrators and OEMs are challenged to work ever more closely together and find a new balance of power for who controls what in the content of an SoC. “We see more and more the design chain driving how our tools work together,” Fra... » read more

Qualcomm Shies Away From High-k At 28nm
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By David Lammers Qualcomm CDMA Technologies said it will not use a high-k/metal gate (HKMG) process for most of the chips it makes at the 28 nm node, sticking with a poly/SiON gate stack. The company described the rationale behind the strategy, which because of Qualcomm’s size will have a major impact on the foundry business, at the 2010 International Electron Devices Meeting (IEDM) held in ... » read more

Version Control Nightmares
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Ed Sperling The rampant re-use of IP and the growing reliance on software to smooth over glitches is creating a nightmare in version control of everything from IP blocks to EDA tools. Version control has always been a problem in SoC design, of course. Tools have to be in sync with engineering teams that are spread across multiple continents and working on different pieces of the design e... » read more

System-Level Technology Conversations Shift To Deployment
By Ann Mutschler - 16 Dec, 2010 - Comments: 0

While much has been achieved to define a system-level design flow, more is still needed. Technology goals vary depending on the perspective of tool providers in terms of what needs to be done to realize the promise of a streamlined tool flow from TLM 2.0 down to GDS II. To many, 2011 will be an interesting year in the system-level design space as conversations with customers have shifted. �... » read more

New 3D Stacking Techniques Emerge
By Ed Sperling - 16 Dec, 2010 - Comments: 0

By Pallab Chatterjee To take advantage of the capabilities of the new technologies, design and circuit architectures in the future will have to be closely coupled with the basic device creation. That shift was the subject of a special session at the recent IEDM conference focusing on the confluence of technology and design. One such area under discussion involved 3D ICs. While a lot of disc... » read more

Troubles At 15nm
By Ed Sperling - 16 Dec, 2010 - Comments: 0

For the better part of the past decade the most advanced companies and the big foundries were targeting 22nm as the bogeyman of chip development. Now it appears the big problems will crop up at 15nm. That means two things. First, the problems that were expected to crop up at 22nm—leakage, electromigration, electrostatic discharge, layout and even verification—appear to have been pushed o... » read more

What’s the cheapest package that will work?
By Javier DeLaCruz - 16 Dec, 2010 - Comments: 0

By Javier DeLaCruz, So often, I come across questions from customers asking what’s the lowest cost package technology that will work. The package by itself should not be the singular focus when considering the lowest-cost solution for a new ASIC. The best approach is to take a few steps back and consider the system and what would work best for that given system, from a variety of standpoint... » read more

Is An FPGA IP Business Model Finally Possible?
By Kurt Shuler - 16 Dec, 2010 - Comments: 0

By Kurt Shuler The IP-SoC conference panel, “IPs on FPGA: Strategy and Vision,” was a learning experience for me. Coming from the software and silicon/ASIC/ASSP worlds, I thought I had a pretty comprehensive view of all the various IP licensing models and their technical implementations. But I learned something new that makes me feel positive about the FPGA’s abilities to finally offer a... » read more

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