February 2011 - Page 3 of 4 - Semiconductor Engineering

Concurrent Design
By Ed Sperling - 11 Feb, 2011 - Comments: 0

The idea of developing software and hardware simultaneously isn't new, but it has taken on renewed urgency in IC design because of growing complexity, including power and proximity issues. Low-Power Engineering captures the perspective of executives at four companies working in this market: Marco Brambilla of STMicroelectronics; Charlie Janac of Arteris; Mike Gianfagna of Atrenta, and Javier De... » read more

Power Panel: IP And Other Key Issues For Future Development
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering chaired a DesignCon panel of low-power experts with Bhanu Kapoor, president of Mimasic; Kesava Talupuru, DV engineer at MIPS; Prapanna Tiwari, CAE manager at Synopsys, and Rob Aitken, an ARM Fellow. What follows are excerpts of their presentations and the panel discussion that followed. Bhanu Kapoor: There are two components of power—dynamic and leakage. Dynamic is wh... » read more

Power Management Trumps Battery Technology
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler The lithium-ion battery has the power to ruin someone’s day, especially when it dies and cannot be charged, not to mention occasional thermal runaways that literally cause explosions. For a technology that is about 30 years old, and approaching its limits, it is mind-boggling that the best brains on the planet haven’t come up with a technological superior alternat... » read more

Healthy Living Electronics Dominated By Power
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Pallab Chatterjee The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living.” In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed toward health-care products. The common theme between all the talks is that health-care is being driven by mobility, information flow, a... » read more

No More Netlist Hacking
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ann Steffora Mutschler Prior to availability of advanced physical verification tools, it was not uncommon for engineering teams to hack netlists. It sounds very clandestine, but was done out of the need to get detailed information on particular areas of the chip suspected to be a problem. Performing electrical rules checks (ERC) to improve the correctness and reliability of IC designs b... » read more

The Missing Pieces In Power Modeling—And Who’s Going To Provide Them
By Ed Sperling - 10 Feb, 2011 - Comments: 0

By Ed Sperling The push to develop power models is growing at each node, and at 22nm it will be virtually impossible to proceed without one or more models for power. Providing these kind of models is easier said than done, however. Creating an accurate power model requires accurate data from all the other pieces on a chip that potentially can affect the power. That includes how third-party ... » read more

Chip-Package-System Co-Design
By Matt Elmore - 10 Feb, 2011 - Comments: 0

By Matt Elmore This year’s DesignCon 2011 featured a multitude of advanced topics pertaining to IC design. One topic that came up repeatedly was chip-package-system (CPS) co-design. In each area of application, from mobile to automotive, IC designers have prioritized the need to analyze the chip, package, and PCB as complete system, rather than independent projects. The old days of margins, ... » read more

Power vs. Accuracy
By Barry Pangrle - 10 Feb, 2011 - Comments: 0

By Barry Pangrle So, how much energy are you willing to expend to be accurate? The question is one that chip designers face more often than they probably realize. The first question really is, ‘How accurate do you need to be?’ Whether it is test coverage, verification coverage, signal-to-noise ratio, or error-correcting codes, the list is seemingly endless. Variability in the environmen... » read more

Tough Road Ahead For Small IP Vendors
By Bhanu Kapoor - 10 Feb, 2011 - Comments: 0

By Bhanu Kapoor The IP business is a difficult one. The vendors who typically supply to larger semiconductor companies face thin margins and different IP requirements to be supported across their customer base. On top of that, no one wants an IP that has not been proven in the field. But if you are looking to be an IP supplier for a low-power SoC that will be manufactured in leading edge p... » read more

Design Impacts of Fully Depleted SOI
By Various Writers - 10 Feb, 2011 - Comments: 0

Xavier Cauchy, digital applications manager at Soitec, considers the design implications of fully depleted SOI technology, including models, low-power techniques for SoCs, and other issues at the 22nm node. “Compelling simulation and silicon data for nanometer scale transistors is becoming available. However, as potential users realize the many interests of this technology, the next question ... » read more

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