February 2011 - Page 4 of 4 - Semiconductor Engineering

Frequently Asked Questions About FD-SOI
By Various Writers - 10 Feb, 2011 - Comments: 0

In a question and answer format, Xavier Cauchy, digital applications manager at Soitec ([email protected]) and François Andrieu, senior research engineer at LETI, raise some of the technical issues surrounding fully depleted SOI technology. The authors compare FD-SOI to FinFETs, describe how non-digital transistors can be handled, and provide a list of references for further reading. » read more

Manufacturing Closure with Calibre InRoute and Olympus-SoC
By Various Writers - 10 Feb, 2011 - Comments: 0

Achieving manufacturing signoff is getting more difficult at each node due to significant manufacturing limitations and variability. This paper from Mentor Graphics describes the physical signoff challenges seen in advanced node designs. It then demonstrates how the Calibre InRoute platform provides faster and more reliable DRC/DFM signoff by using the Calibre verification and DFM platform to d... » read more

Experts At The Table: Concurrent Design
By Ed Sperling - 10 Feb, 2011 - Comments: 0

Low-Power Engineering sat down with Marco Brambilla, ASIC design manager at STMicroelectronics; Charlie Janac, president and CEO of Arteris; Mike Gianfagna, vice president of marketing at Atrenta, and Javier DeLaCruz, director of semiconductor packaging at eSilicon. What follows are excerpts of that discussion. LPE: What is concurrent design and how has the definition changed? DeLaCruz: Th... » read more

The Pain of UPF/CPF
By Ann Mutschler - 10 Feb, 2011 - Comments: 0

Without entering into a debate on the merits of the UPF and CPF, there is a very real and valid concern that designers have today regarding these power intent formats. According to Krishna Balachandran, director of product marketing for low-power verification products at Synopsys, design teams are questioning the validity/correctness of the resulting code. Because they are learning these ... » read more

Metric Pitch BGA And Micro BGA Routing Solutions
By Various Writers - 08 Feb, 2011 - Comments: 0

The following paper provides Via Fanout and Trace Routing solutions for various metric pitch Ball Grid Array Packages. Note: the “metric” dimensions are the ruling numbers. To solve the metric pitch BGA dilemma, one should have a basic understanding of the metric feature sizes for: BGA Ball Sizes and BGA Land Pattern Pad Construction BGA Via Anatomy Trace/Space Trace and Via Routi... » read more

Wafer Demand Grows Despite Supply Chain Jitters
By Joanne Itow - 07 Feb, 2011 - Comments: 0

By Joanne Itow Semiconductor revenue growth broke records in 2010 increasing almost 32% over 2009.  Units grew an equally impressive 25% forcing manufacturers to increase productivity and ramp up additional capacity as quickly as possible. Increased use of leading edge process technology was evident as products processed at 45nm and smaller grew to 16.8% of the total silicon demand in 2010... » read more

Optics Out of Metals at SPIE Photonics West
By Michael Watts - 05 Feb, 2011 - Comments: 0

It was literally and commercially sunny in San Francisco at SPIE Photonics West, held in late January. Lovely weather and an enthusiastic crowd. If you want a large turnout, run a conference in San Francisco in the middle of winter. The conference exhibits took over both major floors of the conference center, and SPIE estimated that nearly 20,000 exhibitors and attendees participated. There ... » read more

Power Is Now No. 1 Concern
By Ed Sperling - 04 Feb, 2011 - Comments: 0

One of the messages that came through loud and clear during DesignCon this week was the concern about power. In every design at advanced nodes, and even in some at older nodes, power has emerged as the top concern. Current leakage is now considered a fact of life at 28nm. It can be managed, but never completely eliminated. And it occurs in both dynamic and standby power, in all modes, and ... » read more

From Your Tour Guide
By Katherine Derbyshire - 04 Feb, 2011 - Comments: 0

Welcome to Semiconductor Engineering's Manufacturing & Design channel. I'm Katherine Derbyshire, your tour guide through the silicon rapids. My background is in materials science, with degrees from MIT and UC Santa Barbara, and I've been following the IC industry since the 1990s, beginning with a stay at Solid State Technology. Through good years and bad, from the first dot com boom to t... » read more

DFM: Out of the Spotlight and Into the Trenches
By David Abercrombie - 03 Feb, 2011 - Comments: 0

By Joe Davis and David Abercrombie The year is 2006. Everywhere you look, the phrase “Design for Manufacturing” or its acronym, DFM, is being brandished as if it were the banner of some brave new army of chip designers. “DFM is the solution to discontinuity issues at 65 nm.” “Traditional boundaries between design and manufacturing will vanish.” Articles and papers discussing DFM ... » read more

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