October 2013 - Page 5 of 10 - Semiconductor Engineering

The Week In Review: Oct. 18
By Mark LaPedus - 18 Oct, 2013 - Comments: 0

By Mark LaPedus & Ed Sperling The problems continue with extreme ultraviolet (EUV) lithography. ASML promised to deliver an 80 Watt power source by year’s end. Now, the company said it only will have a 70 Watt source by mid-2014. “We are focusing on reaching the 70 Watts by the middle of next year,” said Peter Wennink, ASML’s CEO, in a conference call to discuss the company’s res... » read more

3D Printing: Is This A Real Manufacturing Revolution?
By Michael Watts - 17 Oct, 2013 - Comments: 0

As a patterning guy I have been watching the 3D printing story with real interest. Can it deliver or its it hype ? I think that it's an intriguing way to build prototypes and unique parts, but I'm unconvinced that it has any volume manufacturing role. In particular, I have a hard time seeing a business where you can make large numbers of copies of the same manufacturing tool – a key to a “h... » read more

Standards Watch
By Ed Sperling - 17 Oct, 2013 - Comments: 0

This may sound odd to anyone outside of the SoC world, but as more functionality and more components move from PCB to chip—or at least the same package—what’s happening in the standards world is mirroring what’s going on in semiconductor design and manufacturing. The rule of thumb in the standards world is that as new techniques and technologies are introduced, the number of standard... » read more

Approaching IP Quality From Many Angles
By Ann Mutschler - 17 Oct, 2013 - Comments: 0

As SoC design complexity has increased, semiconductor design IP and the industry around it has grown in its level of sophistication. This is great news for the users of that IP whose demands for quality, reliability and other deliverables have also been on the rise. Making sure users have what they need requires close collaboration between the semiconductor foundries, IP providers and of cou... » read more

The “Last Simple Node” And the Internet of Things
By Brian Fuller - 17 Oct, 2013 - Comments: 0

Power, performance and size are key targets that will enable the expected explosion of the Internet of Things (IoT). Today, most observers see the path to that running directly through 16/14nm finFET and below for the node’s ability to manage power and size and boost integration. Geoff Lees isn’t your average observer. The vice president and general manager of Freescale’s microcon... » read more

Following The Yen
By Dan Tracy - 17 Oct, 2013 - Comments: 0

An examination of the installed fab capacity base in Japan shows that total capacity expansion has stalled in recent years due to the consolidation and closures of facilities. The closure and consolidation of 27 facilities between 2009 and 2012 reduced the installed fab capacity in Japan by at least 350,000 200mm equivalent wafers per month. With that said, investments continued in some industr... » read more

Reducing The Tapeout Crunch With Signoff Confidence
By Jean-Marie Brunet - 17 Oct, 2013 - Comments: 1

Crunch time—that last six to eight weeks before tapeout. There’s always too much to do, and too little time. No one wants problems at this stage, because problems mean changes, and changes mean delays. At leading-edge nodes, however, we’re running into some new problems that need new solutions. We all know design rule numbers and complexity are going through the roof as we try to use 1... » read more

Applied-TEL Watch
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

By Mark LaPedus So far this year, the biggest story in the fab tool industry is fairly obvious—Applied Materials recently signed a definitive agreement to acquire rival Tokyo Electron Ltd. (TEL) for about $9.3 billion. The blockbuster announcement will likely be the top story of 2013. Of course, the integration of Applied and TEL will be a challenge. In any case, the Applied-TEL deal is i... » read more

Improving Design Reliability By Avoiding Electrical Overstress
By Various Writers - 17 Oct, 2013 - Comments: 0

Electrical overstress (EOS) is one of the leading causes of IC failures across all semiconductor manufacturers, and is responsible for the vast majority of device failures and product returns. The use of multiple voltages increases the risk of EOS, so IC designers need to increase their diligence to ensure that thin-oxide digital transistors do not have direct or indirect paths to high-voltage ... » read more

Multi-Beam Begins To Shine
By Mark LaPedus - 17 Oct, 2013 - Comments: 0

After years of R&D and promises, multi-beam electron-beam technology is delayed and late to the market. The technology requires more funding and work than previously thought. And generally, the skepticism is running high for the technology. Finally, however, there is a ray of hope, and some momentum, in multi-beam—at least on the photomask front. Seeking to accelerate its multi-beam te... » read more

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