Standards Watch

The number of standards under consideration is rising, but the number of groups working on those standards is shrinking.


This may sound odd to anyone outside of the SoC world, but as more functionality and more components move from PCB to chip—or at least the same package—what’s happening in the standards world is mirroring what’s going on in semiconductor design and manufacturing.

The rule of thumb in the standards world is that as new techniques and technologies are introduced, the number of standards groups explodes because no one fully understands how the various tasks in a complex supply chain will need to be joined together. This is particularly true at the moment in the 450mm world at the moment. As those technologies become more mature, the number of standards groups collapses, the number of standards themselves become more integrated with each other until they’re no longer separate, and the industry moves onto the next set of challenges.

Occasionally there are hiccups in all of this. The dueling power formats in the design world created huge angst for companies designing and verifying chips because they don’t work exclusively with any single vendor’s tools. The result was that bridges needed to be constructed within large chipmakers to solve discrepancies on the verification side, which is by far the most time-consuming part of the design process, and it rippled all the way through manufacturing.

But these kinds of disruptions are few and far between, which is why it’s easy to point to the disruptions caused by those power formats. Those differences were made moot this year with a new IEEE standard. But sometimes it takes time to see where these kinds of discrepancies will appear, particularly in a complex global ecosystem. The stacked-die ecosystem is a case in point. There has been much talk about handling, packaging and testing of the die, how to do it correctly and who’s responsible for when something goes wrong. In fact, the biggest standards issues in stacking die are supply-chain related, and there is no clear resolution because full 3D-ICs using TSVs are still in the test-chip phase.

The same is true with 450mm wafers. There are consortiums formed all over the globe to address issues in handling, polishing, and manufacturing of these large wafers. Once wafers begin rolling out of the fabs we will get a glimpse of whether the standards efforts were successful and what else needs to be addressed.

But once those issues are identified, it’s also incumbent on standards organizations to figure out the best way to merge their efforts and move on to the next problem. Accellera’s acquisition of the Open Core Protocol standard and infrastructure (OCP-IP) is the latest example of how to do this right. Accellera this week acquired the assets of OCP-IP, including management of the current OCP 3.0 standard, which complements some of the other interoperability standards at Accellera. Similarly, Si2 acquired the Compact Model Council in May, which standardized the models used in commercial circuit simulators, including SPICE-class simulation.

These are relatively tight community efforts, though. With stacked die there is a tug of war brewing between the packaging houses and the foundries across multiple continents, all of which are involved in the standards efforts. And with 450mm, there are so many pieces of the supply chain being affected it’s uncertain how and when they will all come together. Nonetheless, it’s in everyone’s best interest to manage the standards effort closely. Too many standards, and too many standards organizations, can wreak havoc in the name of doing the right thing, just as too few can stymy innovation in places where it really counts.

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