August 2014 - Page 3 of 10 - Semiconductor Engineering


IP Subsystems: What Works, What Doesn’t


The [getkc id="81" kc_name="SoC"] landscape has changed substantially over the past decade and so have some of the definitions for aspects of the system—particularly the [getkc id="43" kc_name="IP"] subsystem. “We’ve been at the point for some time for large SoCs that what we thought about as a building block 10 years ago is now too small,” said [getperson id="11489" p_name="Drew Win... » read more

Different Approaches Emerge For Stacking Die


The concept of stacking die to shorten wires, improve performance, and reduce the amount of energy required to drive signals has been in research for at least the past dozen years at both IBM and Intel. And depending upon whom you ask, it could be another 2 to 10 years before it becomes a mainstream packaging approach—if it happens at all. At least part of the confusion stems from how you ... » read more

EDA Suffering Funding Crisis


The EDA industry has been built on venture funding ever since its inception in the early eighties and it is no secret that the big three have relied on a steady stream of startup companies to provide some of the new ideas, to test out new technologies and expand the industry. While there is a lot of research and development that goes on inside the large companies, most of this is related to ... » read more

When To Virtualize, When To Stay In The Real World


Virtualization is all the craze these days. People have virtual personas on LinkedIn, Facebook and Match. I sent my daughter to a Minecraft camp at Stanford where she built virtual worlds while learning programming. Virtualization also plays an important role in chip development, especially when it comes to representing the system environment. There is, however, some crass misinformation out th... » read more

NoC Technology: Saving the Planet, One Chip at a Time


In Silicon Valley, the cliché is that we are using technology to change the world in some meaningful way. However, I made some calculations recently and I found network-on-chip technology is actually contributing to efforts to reduce carbon emissions. SoC designers have become the ultimate energy misers as they strive to make tradeoffs between extending battery life and providing game-chang... » read more

A Novel Approach To Dummy Fill For Analog Designs


With small geometry silicon processes, additional nonfunctional geometric structures are required to maintain layer planarity during the chemical/mechanical polishing (CMP) phase of processing. The automated layout flows to generate such geometries tend to be designed primarily for large system on chip (SOC) digital designs. When applied to mixed-signal layouts, these flows have been seen to ha... » read more

Transaction Debug


SoC design is complex. It involves both software and hardware design that calls for a higher level of abstraction to ensure accurate verification. Transaction-level verification and debug offers this higher abstraction, while staying close to actual hardware signals. Traditionally, its use has been limited by the lack of a better mechanism and database to capture the critical information needed... » read more

Just About Enough Virtual Prototyping


While traveling back to California from the U.K., I had a layover in Chicago, which is probably all too familiar to most United Airlines frequent flyer members. Everything went according to schedule until everyone boarded and the plane still didn’t take off. The pilot explained to us that there was a problem with the hatch for the refueling of the aircraft. We were stuck in the plane for ... » read more

Blog Review: Aug. 20


Ansys’ Bill Vandermark highlights the top five engineering articles of the week. Check out the “Sprouting Baby Monitor.” This may be a sign of what the IoT is really good for. You can also use your cat (or dog or even your kids) to hack your neighbor’s Wi-Fi. Cadence’s Richard Goering says gaps may be narrowing between available tools and what’s needed for 3D-IC design. Now all w... » read more

System Bits: Aug. 19


Revealing the purity of graphene Graphene may be tough, but those who handle it had better be tender, according to researchers from Rice University and Osaka University who have come up with a simple way to spot contaminants given that the environment surrounding the atom-thick carbon material can influence its electronic performance. It is so easy to accidentally introduce impurities into ... » read more

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