February 2016 - Page 5 of 10 - Semiconductor Engineering

LVS Boxing Helps Designers Knock Out Designs Quickly
By Mentor, a Siemens Business - 18 Feb, 2016 - Comments: 0

Keeping up with the constant demand for better, faster design flow performance while preserving the original layout hierarchy of a design can be very challenging during design verification. Designers must constantly manage tradeoffs between performance, database size, and accuracy. In the early design cycle, using the LVS boxing capabilities of Calibre nmLVS to replace incomplete or missing blo... » read more

When And How Should I Color My DP layout?
By David Abercrombie - 18 Feb, 2016 - Comments: 0

Designers working with advanced process technologies that require double patterning often find themselves puzzling over the best way to setup or optimize their design flows to ensure their layouts can be decomposed without time-wasting mistakes. Because manual coloring can be challenging even for experienced engineers, many prefer to use automated coloring solutions. But when is the best time a... » read more

12 Nations Sign Trade Partnership
By SEMI - 18 Feb, 2016 - Comments: 0

By Taylor Sholler Last week, twelve nations across the Pacific-Rim came together to sign the Trans-Pacific Partnership (TPP) in Auckland New Zealand. These economies, making-up roughly 40 percent of the world's GDP, include Australia, Brunei, Canada, Chile, Japan, Malaysia, Mexico, New Zealand, Peru, Singapore, the U.S., and Vietnam. One of the largest trade agreements in history, the TPP will... » read more

Inside Advanced Packaging
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to discuss advanced IC-packaging, the OSAT industry, China and other topics with Ron Huemoeller, vice president of worldwide R&D at Amkor. What follows are excerpts of that conversation. SE: Where are we in advanced IC-packaging today? Huemoeller: We’ve hit the inflection point. Now we are coming to the other side of it. Regarding this need to int... » read more

An Insider’s Guide To Planar And 3D DRAM
By Mark LaPedus - 18 Feb, 2016 - Comments: 0

Semiconductor Engineering sat down to talk about planar DRAMs, 3D DRAMs, scaling and systems design with Charles Slayman, technical leader of engineering at network equipment giant Cisco Systems. What follows are excerpts of that conversation. SE: What types of DRAM do network equipment OEMs look at or buy these days? Slayman: When we look at DRAM, we look at it for networking applicatio... » read more

The Economics Of Moore’s Law
By Imec - 18 Feb, 2016 - Comments: 0

By Marc Heyns I’m very optimistic about the continuation of Moore’s Law. But in saying that, I’m speaking about Moore’s Law purely as an economic law. I believe we’ll be able to offer increasing amounts of functionality at lower and lower costs. And technological innovations as well as advances in design and application will be crucial in realizing this. But I don’t believe a ne... » read more

Reaching For ROI
By Ann Mutschler - 17 Feb, 2016 - Comments: 0

The simplest way to assess power and performance ROI of a chip design is to ask if the chip works and whether it meets the design specifications. But chips can be used in very different ways, and a single chip may have a number of operational modes, so that formula isn't so clear anymore. "Preventing failures is the No. 1 priority when it comes to ROI," said Aveek Sarkar, vice president of p... » read more

Blog Review: Feb. 17
By Jesse Allen - 17 Feb, 2016 - Comments: 0

While there have been successes for 3D-IC, the technology has stalled trying to move into the mainstream market, says Mentor's Michael White. So what has kept it from crossing the chasm? Synopsys' Robert Vamosi takes a look at the US government's latest efforts towards improving cybersecurity. Cadence's Paul McLellan discusses the importance of software-driven hardware verification and th... » read more

System Bits: Feb. 16
By Ann Mutschler - 16 Feb, 2016 - Comments: 0

WW seismic network app UC Berkeley researchers have released a free Android app that uses a smartphone’s ability to record ground shaking from an earthquake, with the goal of creating a worldwide seismic detection network that could eventually warn users of impending jolts from nearby quakes. The app, called MyShake, is available from the Google Play Store and runs in the background with... » read more

Manufacturing Bits: Feb. 16
By Mark LaPedus - 16 Feb, 2016 - Comments: 0

Monoxide chips Two-dimensional (2D) materials are gaining steam in the R&D labs. The 2D materials could enable a new class of field-effect transistors (FETs), but the technology isn’t expected to appear until sometime in the next decade. The 2D materials include graphene, boron nitride and the transition-metal dichalcogenides (TMDs). One TMD, molybdenum diselenide (MoS2), is gaining inter... » read more

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