July 2016 - Page 2 of 12 - Semiconductor Engineering


Advanced Analog And Mixed Signal Design Continues Pushing The Design Envelope


As PCB design has evolved into its present form with extremely complex boards housing high speed circuitry in very small areas, analog and mixed signal (AMS) and high speed analysis can address the latest design challenges. Analog/mixed signal design More and more products incorporate more than just digital circuitry. The vast majority of products now integrate digital and analog circuitr... » read more

Speeding Up The Design Process


A rush to plant a stake in new markets, coupled with uncertainty about how to generate a reasonable return on investment in those markets, is ratcheting up pressure on chipmakers. They now must come up with more customized solutions in less time, frequently in smaller volumes, and with the ability to modify them in shorter time spans if market opportunities shift in unexpected ways. This aff... » read more

Making Verification Easier


SoC design teams increasingly are confronting complexity in the quest to target application segments, but at the same time they are struggling to more quickly reduce risk in their designs while also speed up testing to make sure everything works. Those often-conflicting goals have transformed [getkc id="10" kc_name="verification"] IP from an interesting concept to a must-have tool for advanc... » read more

Why Instrumentation Isn’t Optional


When writing code it is often useful to add informational statements that give an insight into control flow and data management as well as aiding in observation of the actual code at runtime. As such, instrumentation is an important component of code running on a live system. The proliferation of "printf" debug statements, whereby data is output to a console, is testament to this. Sending te... » read more

To Emulate Or Prototype?


FPGA Prototyping is more challenging than emulation. Yet for the time invested in prototype setup, developers are rewarded with a validation platform that is capable of running orders of magnitude faster than emulation. Emulation also has  benefits that appeal especially to design verification engineers. Aside from the completely automated compilation and setup flow, it offers robust debugg... » read more

What’s Next For UVM?


The infrastructure for much of the chip verification being done today is looking dated and limited in scope. Design has migrated to new methodologies, standards and tools that are being introduced to deal with heterogeneous integration, more customization, and increased complexity. Verification methodologies started appearing soon after the release of SystemVerilog. Initially they were inten... » read more

Automating Inter-Layer In-Design Checks In Rigid-Flex PCBs


Flexible PCBs (flex/rigid-flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. As flexible PCB fabrication technology has matured in response to demands for smaller, lighter products, new design challenges have emerged. This paper discusses some of the key challenges to address and also ... » read more

Electronic Design Creation: Overcoming PCB Design Challenges


Think of all the parts that make up the human body: legs, hands, lungs, bones, muscles, and so forth. Yet we are more than mere parts and organs, more than materials and functions. We are human beings. If one part doesn’t work smoothly, all parts are affected. This paper describes how the principle of 'gestalt,' in which an entity is more than the sum of its parts, pertains to the process of ... » read more

IC Validator Programmable EERC Netlist Domain Checking Technology


Traditional visual inspection or manual checking for electrical rule compliance is both time consuming and error prone. A new, comprehensive reliability solution is needed to reduce time to market, improve reliability and ensure longer device operation. This paper introduces IC Validator programmable Extended Electrical Rule Checking (EERC) and categorizes electrical rule checking (ERC) into th... » read more

Stacked Die Changes


Semiconductor Engineering sat down to discuss advanced packaging with David Pan, associate professor in the department of electrical and computer engineering at the University of Texas; Max Min, senior technical manager at Samsung; John Hunt, senior director of engineering at ASE; and Sitaram Arkalgud, vice president of 3D portfolio and technologies at Invensas. What follows are excerpts of tha... » read more

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