January 2017 - Semiconductor Engineering

Manufacturing Bits: Jan. 31
By Mark LaPedus - 31 Jan, 2017 - Comments: 0

Fiber-imprint patterning The École polytechnique fédérale de Lausanne (EPFL)--a research institute/university in Lausanne, Switzerland--has put a new twist in nano-imprint patterning technology. It has devised a way to imprint tiny or nano-metric patterns on hollow polymer fiber. Using a technique called thermal drawing, tiny patterns can be printed on both the inside and the outside of ... » read more

System Bits: Jan. 31
By Ann Mutschler - 31 Jan, 2017 - Comments: 0

Optimizing code To address the issue of code explicitly written to take advantage of parallel computing usually losing the benefit of compilers’ optimization strategies, MIT Computer Science and Artificial Intelligence Laboratory researchers have devised a new variation on a popular open-source compiler that optimizes before adding the code necessary for parallel execution. Charles E. Lei... » read more

BEOL Issues At 10nm And 7nm
By Ed Sperling - 31 Jan, 2017 - Comments: 0

Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for [getentity id="22819" e_name="GlobalFoundries'"] advanced technology development integration unit; Paul Besser, senior technology director at [getentity id="22820" comment="Lam Research"]; David Fried, CTO at [getentity id="22210" e_name... » read more

Power/Performance Bits: Jan. 31
By Jesse Allen - 31 Jan, 2017 - Comments: 0

Microbial nanowires Microbiologists at the University of Massachusetts Amherst report that they have discovered a new type of microbial nanowire, the protein filaments that bacteria use to make electrical connections with other microbes or minerals. The team was motivated by the potential for improved "green" conducting materials for electronics. According to Derek Lovley, professor of... » read more

Rush Hour On The Technology Roadmap
By Mike Gianfagna - 30 Jan, 2017 - Comments: 0

Starting this week, the International Solid State Circuits Conference (ISSCC) will commence at the Marriott in downtown San Francisco. This prestigious conference showcases the latest semiconductor innovations from around the world. Looking at the advance program, one can’t help but notice a shift in the work presented. The conference theme this year is: “Intelligent Chips for a Smart World... » read more

Sigasi: Cleaner VHDL And SystemVerilog
By Ed Sperling - 30 Jan, 2017 - Comments: 0

Hardware engineers always have looked at software tools and methodologies with a certain degree of envy. While the hardware side has embraced the discipline necessary to get products right prior to release, in large part because it's too expensive to fix an error in hardware, the tools and languages are generally clunkier and the methodologies are much more rigid. Like software, they have to in... » read more

Managing Parasitics For Transistor Performance
By Katherine Derbyshire - 30 Jan, 2017 - Comments: 3

The basic equations describing transistor behavior rely on parameters like channel doping, the capacitance of the gate oxide, and the resistance between the source and drain and the channel. And for most of the IC industry's history, these have been sufficient. “Parasitic” or “external” resistances and capacitances from structures outside the transistor have been small enough to discoun... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 27 Jan, 2017 - Comments: 0

Chipmakers Faced with a huge write-down at its nuclear operations, Toshiba is looking to spin off its semiconductor division, which makes NAND. As expected, Toshiba seeks investors in the new company, according to Nikkei. Western Digital (WD) is one potential investor. Foxconn is another possible investor, according to CNBC. Peregrine Semiconductor has rolled out its latest RF SOI process.... » read more

The Week In Review: IoT
By Jeff Dorsch - 27 Jan, 2017 - Comments: 0

Finance Ring, which sells Internet-connected doorbells, security cameras, and other products, received another $109 million in private funding, bringing its total funding to $209 million. DFJ Growth, Goldman Sachs Investment Partners, and Qualcomm Ventures led the Series D round, with participation by Richard Branson and other existing investors. Ring says its products are available in 100 cou... » read more

The Week In Review: Design
By Jesse Allen - 27 Jan, 2017 - Comments: 0

Tools Cadence launched its Sigrity 2017 technology portfolio for PCB power and signal integrity signoff, adding a power topology viewer and editor, library management for power integrity models, and a PCI Express 4.0 compliance kit for checking signal integrity. Memory Spin Transfer Technologies delivered samples of fully functional ST-MRAM (spin transfer magneto-resistive random acces... » read more

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