BEOL Issues At 10nm And 7nm

Experts at the table, part 3: EUV, metallization, self-alignment, ALD, and the limits of copper.


Semiconductor Engineering sat down to discuss problems with the back end of line at leading-edge nodes with Craig Child, senior manager and deputy director for GlobalFoundries’ advanced technology development integration unit; Paul Besser, senior technology director at Lam Research; David Fried, CTO at Coventor; Chih Chien Liu, deputy division director for UMC’s advanced technology development Module Division; and Anton deVilliers, director of patterning technology and senior member of the technical staff at Tokyo Electron. What follows are excerpts of that conversation. To view part one, click here. Part two is here.

SE: Is EUV really saving money for anyone?

Child: If it was a perfect world and everything worked great, yes. We’re unidirectional. The old M1 bi-directional was great. Now we have M1 and M2 to do the same thing. So if you can have EUV do that, 2D, you could remove a lot of masks. It would be a huge benefit. Are we there? No.

Fried: I think we’re very close to implementation on cuts and vias.

Child: We are, and it’s not because the technology is not capable. It’s that everything else isn’t capable. If 7nm and EUV were ready at the same time, there would be a huge difference in cost. But it’s not. Is 5nm going to be ready? Probably? But at that point can we even do bi-directional? We don’t know.

SE: Let’s talk about metallization. We’ve been using the dual damascene process for many generations for lines and vias, and we’ve been using tantalum and tantalum nitride with PVD. Can we extend the current materials and tools to 7nm and beyond, or do we need something new?

Besser: Design rules are blurry. You’re seeing a lot of extension of the copper, and of the PV. Copper will be pushed as far as possible. The extension of the liner has been shown. You’re seeing the first parts come out with a CVD liner. Whether it’s a CVD ruthenium or cobalt liner, you’re probably going to see that at 7nm.

deVilliers: We also need to be cognizant of the enablement of self-alignment. There are tools that are needed for self-alignment. Those systems have unique attributes and properties. They don’t look like a damascene flow anymore. When you’re self-aligning in one or two directions, those self-alignments imply a different set of materials that have different selectivity. It implies a different way to do depositions. And it implies a different way to access the finality of the via that touches the metal because the traditional damascene process is not self-aligned by nature. Those integrations are very different, and they imply different tool sets. The current tool sets are not sufficient to run in self-aligned mode, and to run the type of materials to get low resistance. Without naming specifics, there are systems that have to move in that direction in the back-end space.

SE: What about ALD?

Fried: ALD is more conformal, and because of that, you go back into the problem of cross-sectional area scaling.

Besser: The challenge with ALD is that we’re trying to get to lower k, and with that you’re changing the bonding of the dielectric. You introduce pores so the ALD will penetrate. That’s why that a solution of a PVD barrier with a CVD or ALD liner may be the first step. But aside of just vias, do you see self-alignment coming in anywhere else?

deVilliers: Yes. An extreme example of self-alignment is a 32 pitch on each side made with one litho pass. There are 64 CD’s and they are all self-aligned. 100% of the back end will need some degree of self-alignment to make contact from the position of routing congestion. When you first start the back end, that is where the self-alignment is red hot. And then, as soon as you get into a dimensionality where standard litho can participate, then the degree of self-alignment can drop off.

SE: What does that do to overall cost? Does it compensate for extra time, or is it incremental?

Fried: It depends what the scheme is. Self-alignment is a very broad category. There isn’t one answer for all of them. Memory changed this topic dramatically. The bit costs scaled dramatically when you went to a 3D structure where you’re cutting that many device edges in one process. But there isn’t one answer for every self-alignment scheme.

SE: How far will copper be extended?

Child: It depends on where we end up for 5nm. Clearly it’s copper at 7nm. At a certain pitch and line width, copper starts to be less advantageous than other metals, whether that is cobalt or ruthenium as a bulk fill material. The question is where we end up at 5nm. It’s all intertwined with whether we have EUV and how we are going to pattern it. But at some point, whether it’s 36, 34 or 32nm pitch, cobalt wins, ruthenium starts to win, and that’s when we see the crossover point. We don’t see it now. We will see it in the future. The question is when. Is it 5nm, or is it later?

deVilliers: Yes, the question is what is it. Is it ruthenium, or cobalt, or anything else that’s on the horizon? So in that regard, the majority of the metal used will be copper. If that self-aligned technology gets us out of routing congestion challenges for the first two layers of metal, that’s where we’re talking about whether copper will get us through. All the attention is being given to those one or two levels.

SE: The largest chipmakers can customize those layers in a design. But how about for everyone else?

Child: Yes, if you’re an IDM you can co-optimize for cobalt or whatever you’re using, you can do that. But if you’re offering it across the board for customers, it’s pretty difficult. You have to design that way.

SE: What about variability in resistance, line width and other areas?

Fried: What I hear frequently is companies would take a worse nominal RC if there was a tighter distribution. What they really mean is that if you can fit the entire distribution well inside a previous distribution, then that would be a design benefit. That’s really hard to do. You hear the design community stand up all the time and say, ‘Tighten the bounds and I’ll take a worse nominal.’ The end result is they don’t really want exactly that.

deVilliers: It depends on how you define the middle and back end of line. You get a different answer each time.

Child: And copper is pushing down to lower levels. But some customers are going to fewer local interconnect steps and contact steps and pushing copper lower and lower through novel integration tricks. That’s where cobalt is likely to come in and replace tungsten, and once you have it in there it’s hard to move it out. Ruthenium has a big challenge because its resistivity is flat. We’re all waiting for that first chip to come out.

Related Stories
BEOL Issues At 10nm And 7nm (Part 1)
Lines blur with middle of line as RC delay increases, reliability and yield become more difficult to achieve, and costs skyrocket.
BEOL Issues At 10nm And 7nm (Part 2)
The impact and cost of air gap; reducing RC delay with liner-less approaches and cobalt; where EUV will make a dent…maybe.
Why EUV Is So Difficult
One of the most complex technologies ever developed is getting closer to rollout. Here’s why it took so long, and why it still isn’t a sure thing.
Etching Technology Advances
Atomic layer etch (ALE) moves to the forefront of chip-making technology—finally.

Leave a Reply

(Note: This name will be displayed publicly)