April 2018 - Semiconductor Engineering

Re-Engineering Humanity
By Brian Bailey - 30 Apr, 2018 - Comments: 0

The technology industry is comfortable with trends that increase linearly for decades—and many that follow quadratic curves, also seemingly forever. Moore's Law and the rate of adoption of new technologies are two examples that come to mind. Those same trends can be used to scare or even create panic amongst a less informed general public. Such is the case with Artificial Intelligence (AI)... » read more

What’s Hot At #55DAC
By Valeria Bertacco - 30 Apr, 2018 - Comments: 0

This June at DAC, we will have the opportunity to discuss and learn about key topics that are emerging in the system design and automation community. To start, we have the challenge of designing at the end of silicon scaling and beyond: devices, design complexity and verification. On Monday, there will be a tutorial on designing at advanced technology nodes, followed by an invited session o... » read more

Partitioning Becomes More Difficult
By Ann Mutschler - 30 Apr, 2018 - Comments: 0

The divide-and-conquer approach that has been the backbone of verification for decades is becoming more difficult at advanced nodes. There are more interactions from different blocks and features, more power domains, more physical effects to track, and far more complex design rules to follow. This helps explain why the number of tools required on each design—simulation, prototyping, em... » read more

Advanced 3D Design Technology Co-Optimization For Manufacturability
By Yu De Chen - 30 Apr, 2018 - Comments: 0

By Yu De Chen, Jacky Huang, Dalong Zhao, Jiangjiang (Jimmy) Gu, and Joseph Ervin Yield and cost have always been critical factors for both manufacturers and designers of semiconductor products. It is a continuous challenge to meet targets of both yield and cost, due to new device structures and the increasing complexity of process innovations introduced to achieve improved product performanc... » read more

The Week In Review: Manufacturing
By Mark LaPedus - 27 Apr, 2018 - Comments: 0

Chipmakers As reported, Intel is struggling at 10nm. Intel already has encountered some difficulties, as the chip giant late last year pushed out the volume ramp of its new 10nm process from the second half of 2017 to the first part of 2018, according to analysts. Intel continues to struggle with 10nm, and has delayed the volume ramp again, according to multiple reports. During its earnings... » read more

The Week In Review: Design
By Jesse Allen - 27 Apr, 2018 - Comments: 0

M&A Alibaba acquired C-Sky Microsystems, which focuses on 32-bit embedded CPU IP cores in both low power and high performance varieties, as well as SoC and MCU platforms. Founded in 2001, the Hangzhou, China-based C-Sky previously received investment from Alibaba, and the two companies collaborated on a hardware and software platform for IoT and cloud integration. The deal comes on the hee... » read more

The Week in Review: IoT
By Jeff Dorsch - 27 Apr, 2018 - Comments: 0

Cybersecurity Cybersecurity concerns continued to generate news this week. Symantec reported a corporate espionage hacking campaign against manufacturers of medical supplies, dubbing the efforts “Orangeworm.” The hackers have attacked 24 or more targets this year, and almost 100 since 2015, according to the security software and services firm. Meanwhile, the House Energy and Commerce Co... » read more

The Great Chip Shakeup
By Ed Sperling - 26 Apr, 2018 - Comments: 2

Facebook, Alibaba, Google, Apple and Samsung are all designing their own chips. So are Cisco and Huawei. So what exactly does this mean for big chipmakers and the semiconductor ecosystem? While your first impulse might be to draw a straight line between Qualcomm's decision to cut 1,500 jobs and reports about giant systems companies developing chips in-house, it's not clear there is any corre... » read more

Interface DRC Can Streamline Chip-Level Interface Physical Verification
By James Paris - 26 Apr, 2018 - Comments: 0

In most design companies, the chip-level physical implementation teams responsible for design floorplanning in place and route (P&R) environments also manage top-level physical verification from the early floorplanning stages through tapeout. In early floorplanning stages, blocks placed in the chip-level floorplan are usually still under development. Merging these incomplete blocks with the... » read more

Neural Nets In ADAS And Autonomous Driving SoC Designs
By Kurt Shuler - 26 Apr, 2018 - Comments: 0

Automotive electronics has ushered in a new wave of semiconductor design innovation and one new technology gaining a lot of attention is neural networks (NNs). Advanced driving assistance systems (ADAS) and autonomous car designs now rely on NNs to meet the real-time requirements of complex object-recognition algorithms. The concept of NNs has been around since World War II, promising a futu... » read more

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