April 2018 - Page 2 of 13 - Semiconductor Engineering

Bugs With Long Tails Can Be Costly Pests
By Gajinder Panesar - 26 Apr, 2018 - Comments: 0

I don’t think Van Gogh was considering high performance computing or server architecture, but he made a lot of sense when he said "great things are done by a series of small things brought together." A series of very small things can, and do, create big things: that’s the fundamental premise of long-tail marketing: Amazon, for one has built a strong business from selling millions of niche i... » read more

Inside UVM, Take Three
By Vatsal Choksi - 26 Apr, 2018 - Comments: 0

The reason why UVM came up with such phases is because synchronization among all design-testbench was necessary. Using Verilog and VHDL, verification engineers did not have facilities such as clocking block or run phases. Now, it is very important that the time at which test vectors applied from test-bench reaches the Design Under Test(DUT) at the same time. If timing for different signals vari... » read more

Why Your FPGA Synthesis Flow Requires Verification
By Tom Anderson - 26 Apr, 2018 - Comments: 0

When you think about it, logic synthesis is a vital but rather intimidating part of modern chip design. This process takes a high-level description of intended functionality, written in an RTL language that looks more like software than hardware, and implements it using the low-level building-block library of an ASIC or FPGA device. The resulting gate-level netlist must meet a variety of requir... » read more

Hidden Costs Of Shifting Left
By Brian Bailey - 26 Apr, 2018 - Comments: 0

The term "Shift Left" has been used increasingly within the semiconductor development flow to indicate tasks that were once performed sequentially must now be done concurrently. This is usually due to a tightening of dependences between tasks. One such example being talked about today is the need to perform hardware/software integration much earlier in the flow, rather than leaving it as a sequ... » read more

Deep Learning And The Future
By Mike Gianfagna - 26 Apr, 2018 - Comments: 1

Following up from my last post on our deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation,” I’d like to take a glimpse into the future. Like many such discussions, it’s often useful to take a look back first to try and make sense out of what is to come.  That’s essentlially what our keynote speaker, Ty Garibay, did at the event. Ty is the CTO... » read more

Tech Talk: FPGA RTL Checking
By Ed Sperling - 26 Apr, 2018 - Comments: 3

Tobias Welp, software architect and engineering manager at OneSpin Solutions, explains how to ensure the RTL created by design engineers matches what shows up in an FPGA. https://youtu.be/0N1PDYyq0dY » read more

Design Flows At 5nm And Beyond
By Mark Richards - 26 Apr, 2018 - Comments: 0

It’s probably the first time that you’ll ever hear an old (well, old-ish!) person say this, but things were easier back in my day. 40 nanometers was the most advanced node that I ever designed SoCs at and, although it wasn’t easy back then, it pales against the myriad of challenges facing designers today. Back then, compartmentalization of function and roles was relatively easy. We do ... » read more

More Nodes, New Problems
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

The rollout of leading-edge process nodes is accelerating rather than slowing down, defying predictions that device scaling would begin to subside due to rising costs and the increased difficulty of developing chips at those nodes. Costs are indeed rising. So are the number of design rules, which reflect skyrocketing complexity stemming from multiple patterning, more devices on a chip, and m... » read more

Tech Talk: Improving Verification
By Ann Mutschler - 26 Apr, 2018 - Comments: 0

Frank Schirrmeister, senior group director for product management and marketing at Cadence, discusses how to verify different use cases, focusing on software, low-power designs, connectivity, and a variety of end markets. https://youtu.be/gK-0vmIWxJs » read more

Different Shades Of Prototyping And Ecosystems: System Development At CDNLive 2018
By Frank Schirrmeister - 26 Apr, 2018 - Comments: 0

Because of its unique great user interactions, my favorite EDA event of the year is the kickoff of our yearly series of CDNLive user conferences in Silicon Valley. This year blew out all my expectations. We had a dozen presentations in the Systems Track that I was sharing, 11 of them from customers and partners underlining the use model versatility of emulation, the hardware ecosystem for 5G, a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy