April 2018 - Page 3 of 13 - Semiconductor Engineering

EDA In The Cloud
By Brian Bailey - 26 Apr, 2018 - Comments: 4

Semiconductor Engineering sat down to discuss the migration of EDA tools into the Cloud with Arvind Vel, director of product management at ANSYS; Michal Siwinski, vice president of product management at Cadence; Richard Paw, product marketing manager at DellEMC, Gordon Allan, product manager at Mentor, a Siemens Business; Doug Letcher, president and CEO of Metrics, Tom Anderson, technical marke... » read more

Multi-Die Packaging And Thermal Superposition Modeling
By eSilicon - 25 Apr, 2018 - Comments: 0

Packaging density, electrical performance and cost are the primary factors driving electronic package architectures for high-performance server markets. Considerations such as thermal performance and mechanical reliability are equally important but tend to be addressed later in the design cycle. Presented in this paper is a historical view of the packaging trends leading to the current multi-di... » read more

Resets And Reset Domain Crossings In ASIC And FPGA Designs
By Aldec - 25 Apr, 2018 - Comments: 0

This white paper explains Reset-related ASIC and FPGA design issues as well as outlines commonly-used design techniques leading to safe reset implementations. It goes on to explain about Reset Domain Crossing effects and methods to mitigate their influence on design. LINT tools provide valuable help for designers in Resets and Reset Domain Crossings verification. To download this paper, clic... » read more

8 Checks That Every PCB Designer Needs To Achieve Electrical Sign-Off
By Mentor, a Siemens Business - 25 Apr, 2018 - Comments: 0

Automate electrical design rule checking (DRC) for fast, cost-effective PCB design verification. These eight rules apply regardless of your PCB layout tool or level of expertise. To read more, click here. » read more

Synopsys’ Vision For The New Wave Of Chip Design
By Synopsys - 25 Apr, 2018 - Comments: 0

Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

Next EUV Issue: Mask 3D Effects
By Mark LaPedus - 25 Apr, 2018 - Comments: 6

As extreme ultraviolet (EUV) lithography moves closer to production, the industry is paying more attention to a problematic phenomenon called mask 3D effects. Mask 3D effects involve the photomask for EUV. In simple terms, a chipmaker designs an IC, which is translated from a file format into a photomask. The mask is a master template for a given IC design. It is placed in a lithography scan... » read more

New Market Drivers
By Brian Bailey - 25 Apr, 2018 - Comments: 0

Semiconductor Engineering sat down to discuss changing market dynamics with Steve Mensor, vice president of marketing for [getentity id="22926" e_name="Achronix"]; Apurva Kalia, vice president of R&D in the System and Verification group of [getentity id="22032" e_name="Cadence"]; Mohammed Kassem, CTO for [getentity id="22910" comment="efabless"]; Matthew Ballance, product engineer and techn... » read more

AI Accelerating Discovery
By Joanne Itow - 25 Apr, 2018 - Comments: 0

In early April 2018, the Materials Research Society held their spring meeting and exhibit at the Phoenix, Arizona convention center. With more than 110 symposium presentations, it was difficult to select which sessions to attend. But one forum caught my eye, “AI for Materials Development”. These days AI seems to be everywhere. As we all speculate about the impact of AI on autonomous driv... » read more

Blog Review: Apr. 25
By Jesse Allen - 25 Apr, 2018 - Comments: 0

Mentor's Cristian Filip digs into SerDes design with a focus on the adoption and evolution of Channel Operating Margin (COM) as a tool for ensuring compliance of high-speed designs and why it's useful even if its mathematical procedure might be intimidating at the beginning. Cadence's Paul McLellan explains the importance of IBIS and AMI standards for SerDes design and why the upcoming DDR5 ... » read more

Manufacturing Bits: April 24
By Mark LaPedus - 24 Apr, 2018 - Comments: 0

Super electron guns The Department of Energy’s SLAC National Accelerator Laboratory is developing a new type of electron gun based on superconducting technology. The new superconducting electron gun recently produced its first beam of electrons, according to SLAC. The technology is being developed for future high-energy X-ray lasers and ultra-fast electron microscopes. Electron guns a... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy