Thermal limits and benefits offered by different packaging options.
Packaging density, electrical performance and cost are the primary factors driving electronic package architectures for high-performance server markets. Considerations such as thermal performance and mechanical reliability are equally important but tend to be addressed later in the design cycle. Presented in this paper is a historical view of the packaging trends leading to the current multi-die package options. Particular attention must be placed on the thermal limitations and benefits offered by each design. Since multi-die packages have many junctions of interest, a method for characterizing the package with arbitrary power conditions is required. A superposition method, using a matrix approach, is presented that will enable the end-user to investigate the effects of power levels on junction temperatures. Experimental data measured on a 2.5D package were taken to demonstrate the matrix approach for predicting junction temperature based on an independent power map. The agreement between the matrix model and data generated by an independent power map is within 8%.
To read more, click here.
Companies battle it out to get artificial intelligence to the edge using various chip architectures as their weapons of choice.
Bulk CMOS, FD-SOI and finFETs all on tap as big players vie for differentiation. But where will chipmakers go after 28nm?
Experts at the Table, Part 1: Impact on the supply chain, who’s using advanced packaging, and the cost of packaging versus device scaling.
Consortiums seek ways to ensure interoperability of hardened IP as way of cutting costs, time-to-market, but it’s not going to be easy.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
AI-enabled systems are being designed to process more data locally as device scaling benefits decline.
Chips will cost more to design and manufacture even without pushing to the latest node, but that’s not the whole story.
Access to source code makes it attractive for custom applications, but gaps remain in the tool flow and in software.
Growing volume of data and limited improvements in performance create new opportunities for approaches that never got off the ground.
Semiconductor design lags behind other industries in adopting the cloud, but there could be some good reasons for that. Change is difficult.
Behind closed doors: Semiconductor executives talk about the bugs they fear the most and the problems solving them.
While CPUs continue to evolve, performance is no longer limited to a single processor type or process geometry.
New data flow, higher switch density and IP integration create issues across the design flow.
 |
 |
 |
 |
 |
 |
 |
 |
 |
|
Leave a Reply