May 2018 - Page 2 of 12 - Semiconductor Engineering

The Week In Review: Manufacturing
By Mark LaPedus - 25 May, 2018 - Comments: 0

Chipmakers GlobalFoundries has announced that its 22nm FD-SOI technology platform has been certified to AEC-Q100 Grade 2 for production. As a part of the AEC-Q100 certification, devices must withstand reliability stress tests for an extended period of time and over a wide temperature range in order to achieve Grade 2 certification. Presto Engineering has joined GlobalFoundries’ ecosystem ... » read more

The Week in Review: IoT
By Jeff Dorsch - 25 May, 2018 - Comments: 0

Finance Orbbec of Shenzhen, China, a developer of motion sensing technology, raised more than $200 million in Series D funding led by Ant Financial. Also participating in the new round were SAIF Financial, Green Pine Capital Partners, R-Z Capital, and Tianlangxing Capital Partners. Established in 2013, Orbbec develops 3D sensors for applications in facial recognition, gesture recognition, robo... » read more

The Week In Review: Design
By Jesse Allen - 25 May, 2018 - Comments: 0

Tools & IP Cadence and National Instruments are teaming up with the aim of improving the semiconductor development and test process. The two companies are jointly working on common transistor models to ensure consistent simulation behavior between NI AWR Microwave Office circuit design software and the Cadence Spectre simulation platform. Cadence also launched the Virtuoso RF Solution for ... » read more

The 3D Printing Revolution
By Ed Sperling - 24 May, 2018 - Comments: 1

3D printing always has been intriguing. More recently, it has become truly useful. And in the near future, it will become increasingly controversial. There are videos on YouTube documenting entire homes that are being printed in as little as 8 hours, priced as low as $4,000. So while there is a lot of buzz about AI eliminating jobs, 3D printing could add become another significant threat. ... » read more

Commoditizing Constraints
By Brian Bailey - 24 May, 2018 - Comments: 2

Preparing articles for Semiconductor Engineering involves talking to a lot of people and then trying to fit their statements together in a way that is logical and fair. Sometimes a subject will come up in one of these calls that is not really on topic, but is still interesting. One such incident happened this week while doing research for the Verification 3.0 article. The topic was constrain... » read more

Making Declarative Modeling Modular: Portable Stimulus Introduces Dynamic Constraints
By Matthew Ballance - 24 May, 2018 - Comments: 0

Naturally, Accellera’s Portable Stimulus Standard (PSS) supports the powerful capabilities of advanced verification techniques that are well-known in the industry today, including object-oriented composition and constrained-random stimulus. But the PSS also supports a new constraint capability, called dynamic constraints. Dynamic constraints support the critical mission of the PSS by makin... » read more

Electronic System-Level Design: Are We There Yet?
By Frank Schirrmeister - 24 May, 2018 - Comments: 0

I am writing this while attending NI Week in Austin and am admittedly wowed by National Instruments’ open test platform. NI Week’s theme is “Developing the Future Faster.” The Tuesday keynote included guest speakers from Mazda, Honeywell, and NXP, and these were great examples of system-level design of different scopes, from cars to distributed systems to chips enabling them. Personally... » read more

A Combined Design And Verification Flow For Safety-Critical Designs
By Tom Anderson - 24 May, 2018 - Comments: 0

By Tom Anderson and Srikanth Rengarajan I welcome my co-author for today’s post, Srikanth Rengarajan, vice president of product and business development from Austemper Design Systems. We would like to focus on safety-critical designs, a topic very much in the news these days because of the public’s fascination with autonomous vehicles. This consumer category now joins medical electron... » read more

Analog Migration Equals Redesign
By Ann Mutschler - 24 May, 2018 - Comments: 1

Analog design has never been easy. Engineers can spend their entire careers focused just on phase-locked loops (PLLs), because to get them right the functionality of circuits need to be understood in depth, including how they respond across different process corners and different manufacturing processes. In the finFET era, those challenges have only intensified for analog circuits. Reuse, fo... » read more

Get Ready For Verification 3.0
By Brian Bailey - 24 May, 2018 - Comments: 0

Jim Hogan, managing partner of Vista Ventures, LLC, is perhaps the best-known investor in the EDA space. Recently, he has been focusing time and attention on verification startups, including cloud technology company Metrics, and Portable Stimulus pioneer Breker Verification Systems. This adds to his longer-term commitment to formal verification with OneSpin Solutions. These companies are part ... » read more

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