September 2018 - Page 2 of 12 - Semiconductor Engineering

Is Cloud Computing Suitable for Chip Design?
By Brian Bailey - 27 Sep, 2018 - Comments: 2

Is semiconductor design being left behind in a cloud-dominated world? Finance, CRM, office applications and many other sectors have made the switch to a cloud-based computing environment, but the EDA industry and its users have hardly started the migration. Are EDA needs and concerns that different from everyone else? We are starting to see announcements from EDA companies, but few cheerleaders... » read more

The Revenge Of The Digital Twins
By Frank Schirrmeister - 27 Sep, 2018 - Comments: 0

How do we verify artificial intelligence? Even before “smart digital twins” get as advanced as shown in science fiction shows, making sure they are “on our side” and don’t “go rogue” will become a true verification problem. There are some immediate tasks the industry is working on—like functional safety and security—but new verification challenges loom on the horizon. As in pr... » read more

Betting Big On Discontinuity
By Ed Sperling - 27 Sep, 2018 - Comments: 0

Wally Rhines, president and CEO of Mentor, a Siemens Business, sat down with Semiconductor Engineering to talk about the booming chip industry, what's driving it, how long it will last and what changes are ahead in EDA and chip architectures. What follows are excerpts of that conversation. SE: The EDA and semiconductor industries are doing well right now. What's driving that growth? Rhine... » read more

Giving Cars A Bird’s-Eye View
By Farhad Fallahlalehzari - 27 Sep, 2018 - Comments: 0

Will the world be a better place in which to live by having autonomous cars driving around us? Or would it be unsafe and scary? Maybe someone was asking such a question even when the first steam-powered automobile capable of human transportation was built in 1769 [1]! As a person who likes driving, I wouldn’t like to have a ‘fully’ autonomous car, but I would like to get some assistanc... » read more

Domain Crossing Nightmares
By Brian Bailey - 27 Sep, 2018 - Comments: 1

Semiconductor Engineering sat down to discuss problems associated with domain crossings with Alex Gnusin, design verification technologist for Aldec; Pete Hardee, director, product management for Cadence; Joe Hupcey, product manager and verification product technologist for Mentor, a Siemens Business; Sven Beyer, product manager design verification for OneSpin; and Godwin Maben, applications en... » read more

56G 7nm SerDes: Eyewitness Account
By Mike Gianfagna - 27 Sep, 2018 - Comments: 0

High-performance SerDes represents critical enabling technology for advanced ASICs. This star IP block finds application in many networking and switching designs as well as other high-performance applications. So, when a new high-performance SerDes block hits the streets, it’s real news. eSilicon has been enjoying the spotlight on such an event. We recently announced silicon validation of our... » read more

Using CAA And DFM Scoring To Improve Manufacturing Success
By Mentor, a Siemens Business - 26 Sep, 2018 - Comments: 0

Critical area analysis and design for manufacturing scoring both offer designers actionable information they can use to improve their designs to prevent low-yield issues in the foundry. At the same time, they provide the foundry with information they can use for process improvement. Learn how fabless designers, foundries, and integrated device manufacturers can all benefit from addressing manuf... » read more

Tineola: Taking A Bite Out Of Enterprise Blockchain
By Synopsys - 26 Sep, 2018 - Comments: 0

Enterprise blockchain adoption reached a fever pitch in 2018, but the security community has been late to the game of securing these platforms against attacks. We wanted to bridge the gap between the widespread use of enterprise blockchain platforms and the limited knowledge we have about their security by exploring the leading enterprise platform, Hyperledger Fabric, from the perspective of a ... » read more

Accelerate SoC Simulation Time of Newer Generation FPGAs
By Aldec - 26 Sep, 2018 - Comments: 0

Comprehensive verification that can be provided by HDL simulators is good, but not ideal. What is necessary is a faster, safer, and more thorough verification environment that combines the robustness of an HDL simulator with the speed of FPGA prototyping boards. The goal is to put together the power of these two verification methodologies into one platform. Read more. » read more

Analog Reliability Analysis for Mission-Critical Applications
By Cadence - 26 Sep, 2018 - Comments: 0

Rapidly increasing electrical content in automobiles is driving the need for revolution in analog integrated circuit (IC) design methodology. Compared to designing for consumer electronics, designing for mission-critical applications—industrial, medical, space, and automotive—requires a different approach to reliability analysis. We will explore how reliability analysis needs to change for ... » read more

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