February 2019 - Page 2 of 12 - Semiconductor Engineering

The Rapid Rise Of RISC-V
By Andy Gothard - 28 Feb, 2019 - Comments: 0

The first RISC-V Summit, which took place last month in Santa Clara, CA, appears to be a watershed for the RISC-V ecosystem. The technology is maturing and the ecosystem is growing fast – and that was reflected in the nature of the presentations and news announcements we saw. The accent has started to move to how the technology will be used in real life. UltraSoC’s announcement of a har... » read more

Can Debug Be Tamed?
By Brian Bailey - 28 Feb, 2019 - Comments: 0

Debug consumes more time than any other aspect of the chip design and verification process, and it adds uncertainty and risk to semiconductor development because there are always lingering questions about whether enough bugs were caught in the allotted amount of time. Recent figures suggest that the problem is getting worse, too, as complexity and demand for reliability continue to rise. The... » read more

Reverse Debug
By Ed Sperling - 28 Feb, 2019 - Comments: 0

Chun Chan, product applications engineering director at Synopsys, talks with Semiconductor Engineering about testbench debug and how adding time markers can speed time to signoff. https://youtu.be/tx_89M1bq3Q » read more

A Conference For The Ages
By Mike Gianfagna - 28 Feb, 2019 - Comments: 0

The International Solid-State Circuits Conference (ISSCC) was held recently in its permanent location at the San Francisco Marriott Marquis. eSilicon had the honor of both presenting our SerDes capabilities and demonstrating the technology as well. More about that later. First, I’d like to examine the institution called ISSCC. The first ISSCC was held in 1954 in Philadelphia. Yes, 1954, that�... » read more

Optimizing Deep-Learning Inference For Embedded Devices
By Silexica - 27 Feb, 2019 - Comments: 0

Deep artificial neural networks (ANNs) have emerged as universal feature extractors in various tasks as they approach (and in many cases surpass) human-level performance. They have become fundamental building blocks of almost every modern artificially intelligent (AI) application, from online shop recommendations to self-driving cars. This whitepaper highlights how different challenges relat... » read more

Smoke Testing A High-Level Synthesis Design
By Mentor, a Siemens Business - 27 Feb, 2019 - Comments: 0

Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after High-Level Synthesis (HLS), teams need a way to quickly ensure that the newly-generated RTL is functionally the same as the original untimed C++. They don’t want to create an RTL testbench in order to make this comparison. What teams need is an automated smoke test to quickly make the... » read more

How to Connect Questa VIP to the Processor Verification Flow
By Codasip - 27 Feb, 2019 - Comments: 0

Learn how to incorporate Questa VIP into your existing RISC-V verification flow. This step-by-step tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process. Read more here. » read more

Efficient Low-Cost Implementation of NB-IoT for Smart Applications
By Synopsys - 27 Feb, 2019 - Comments: 0

NB-IoT is an emerging technology for narrowband wireless communication standardized by 3GPP. It has been designed with a focus on minimizing end-user equipment processing requirements and power consumption to enable the massive deployment of low-cost devices for a broad range of smart applications. This white paper highlights the key challenges of NB-IoT modem design. It proposes a hardware/sof... » read more

Unified Compression and LBIST in a Physically Aware Environment
By Cadence - 27 Feb, 2019 - Comments: 0

Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

Why 56Gb/s And 112Gb/s SerDes Matter In Our Daily Social-Media-Driven Lives
By eSilicon - 27 Feb, 2019 - Comments: 0

Hyper-scalers and service providers are moving from 100GbE to 400GbE Ethernet rates and beyond. Wireline and wireless networks are driving new architectures to support the move from 4G LTE to 5G infrastructure. These transitions are driven by the increasing global IP traffic as the world becomes more connected and digital. At the same time, the decentralization of the cloud and data centers are... » read more

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