3D Brings Test Into Fashion

By Ann Steffora Mutschler
As integral and critical as test is to the success of an SoC, it isn’t always one of those topics in semiconductor design that seems fashionable.

But as Bassilios Petrakis, director of product marketing for test products at Cadence pointed out, “[Test] is not in fashion, but when we hit one of those brick walls then suddenly we have to think how we are going to solve it. You’re on autopilot until you hit a disruption, and 3D represents a disruption.”

Whether it is memory stacked on logic, which is most common today, or stacking multiple logic die on top of each other vertically with through silicon vias (TSVs), both approaches are complicated and require more infrastructure than traditional SoCs.

Yervant Zorian, a Synopsys fellow and chief architect, noted that we have always dealt with multiple chips—but the multiple chips that we dealt with previously were packaged chips. “Having packaged chips on a board allowed us to test the chips fully upon packaging when they are on the wafer. And also, after being packaged to give the full quality chip, proven and warrantied to the board-level team to assemble it on the board. Now that’s all good when a die is packaged—a package protects it from further defectively. However, with 3D stacks or 2.5D interposers or some other advanced packaging technologies we are dealing with there is bare die that is unpackaged so the whole issue starts with that.”

So even though the bare die are fully tested, they are prone to defectively during assembly, mounting, transportation. “Whatever you do between the production of that die up through the time it is assembled with the rest of the dies there is this defectivity magnet situation where certain things happen to it and therefore we need to retest it after it’s been assembled—whether it is two dies, four dies, at every stage you need to test it again to make sure that nothing is damaged,” he added.

Clearly, the test challenges with stacked die include the need to test things at multiple points during fabrication and assembly, Petrakis said. “Then there is a big question about how much testing is required. With test there is cost and what do you forgo and what do you actually test.”

There are two schools of thought here, he noted. One is to use the normal manufacturing test type of approaches such as implanting test circuitry as is normally done and testing each die separately. “You make sure that you apply all the tests and then you know you probably have good die to work with. ‘Probably’ is a good term because you never know.”

Then, if the design will use through-silicon vias, what is the best approach to test and how do you get access to the test interface? “On a normal chip you just go to the pads and you say, ‘These are the test pads,’ and you target those. On a TSV-based design there is a lot of talk about landing probes, but the dimensions are so small that there is fear that they are going to be damaged,” he added.

It’s not all doom and gloom with stacked die, though. “The fun comes in when you start stacking logic die,” asserted Stephen Pateras, product marketing director for Mentor Graphics’ Silicon Test Solutions group. “In the case where you had a single logic die you had full access to it. If there were any test pins and memories that needed to be accessed directly even though they are stacked, you’re going through the BiST, the JEDEC standard interface, so you don’t have to worry about accessing the DRAMs directly. But with stacked logic die, now presumably you want to test pieces of a logic die. You want to test the interconnect between them, so you need access each of those logic die independently somehow. Generally you don’t have access to them, because if they are stacked vertically the idea is that the bottom die will be the one that is connected to the package and the other die are connected to each other. So there may be neighbors top or bottom in that stack. That’s where we need to have a way of going through the stack to get access to those die for test so you need some kind of test access architecture that makes use of the TSVs.”

At the foundation of such a test access architecture is the proposed IEEE P1838 standard, which gives just such access.

Zorian explained that IEEE P1838 complements the work that was done previously with JTAG 1149.1 and IEEE 1500, whereby JTAG was for the chips on the board and 1500 was for the cores in the SoC. “P1838 is for the dies in a 3D structure to talk to those dies. You need an access port and this access port cannot be JTAG. It cannot be 1500, but it can be something between the two and very complementary to those working hand-in-hand coherently with the first two standards to handle the new multi-dies in a package. P1838 will allow us to know exactly what that test bus is. The seven-bit communication bus proposed today will communicate the test related functions between one die to the other, from that die to the next and so on.”

By the time 3-D becomes prominent it is expected that P1838 will be ratified as an IEEE standard.

Further, Cadence’s Petrakis noted that the idea behind p1838 is isolation. “How do we isolate one die from the others such that we can test it internally without disturbing anything else? Then it’s not quite really disturbing it. It’s really a matter of true isolation. You do not want any foreign signals or unknown traditions to affect the testing that you are doing. The isolation is that we put the chip in a mode where it only sees data coming in and out from itself. In other words, the application of test reading the results back is not influenced by anything else.”

The looming cost concern
Amidst the technical challenges of 3D and 2.5D stacked die is the discussion surrounding who will pay for all of this extra testing.

Synopsys’ Zorian said, “The two stops in test that we used to have, which is testing the chip at the wafer level and testing the chip post-package, will still be there. But now we introduce intermediate steps so suddenly we need to do more test in between. When I have two dies together, three dies together—these are the prevalent situations where we need to test them. And there is a cost associated with it because it is after the die has been produced, so you cannot cost-wise expect the die producer that is the chip manufacturer to do that. It is a packaging-oriented cost because it happens later on during the stages of pulling those dies together. It depends who will be doing it and therefore who will pay for it.”

At this point, it seems that the cost will not fall to the die producer, but it depends on how the business model develops—especially because several chip manufacturers and foundries have expressed interest in being part of this ecosystem. “Whether it is TSMC, GlobalFoundries or otherwise, if they are doing it then of course it will be the last stage, because it’s not the wafer manufacturing stage or the wafer testing stage. It is one stage after that.”

However the situation turns out, the rising wave of 3D manufacturing and test is causing ripples throughout the entire ecosystem.