3D Neuromorphic Architectures

Matrix multiplication is a critical operation in conventional neural networks. Each node of the network receives an input signal, multiplies it by some predetermined weight, and passes the result to the next layer of nodes. While the nature of the signal, the method used to determine the weights, and the desired result will all depend on the specific application, the computational task is simply a dot product of the signal and weight matrices.

One proposal for implementing such calculations with memristor devices uses a crossbar array with ReRAM or phase-change memory elements at the intersections between row and column electrodes. The weights are stored in the conductance of each node. Ohm’s Law gives a current I as the product of the conductance (1/R) and an applied voltage (V), and Kirchoff’s Law states that currents from multiple nodes can be added together.

While this approach is conceptually simple, the enormous number of connections needed for systems that can solve practical problems introduces significant challenges. Manufacturers will need integration schemes that can manage thousands of inputs, with potentially millions of synaptic connections. If, as researchers hope, neuromorphic designs are able to break the von Neumann bottleneck, the datasets being manipulated are likely to get still larger. Because of the large number of connections required, some form of 3D integration is sure to be needed for neuromorphic computer architectures.

3D integration promises high density and rapid parallel calculations. On the other hand, the large number of tightly packed connections needed for such a scheme introduces a number of potential concerns. Heat management is an important issue for 3D integration generally. With ReRAMs, though, the transition between the high and low resistance states is accompanied by substantial joule heating. In phase change memories, the transition between ON and OFF states explicitly depends on a thermally-driven change in structure. Both circuit designers and package engineers need to be aware of the potential for thermal crosstalk between adjacent lines.

IBM’s True North chip, with 1 million neurons and 256 million synapses, offers a preview of the requirements such designs might face. IBM uses injection-molded solder connections between layers of a chip stack. Currently placed at a 50 micron pitch, they will need to reach a 10 micron flip-chip pitch to support high-I/O neuromorphic applications. Electrical crosstalk, electromigration, and mechanical stress must all be accounted for in the solder composition and insulating dielectrics.

A true neuromorphic architecture would not simply calculate weights for connections in an existing network, but, like biological brains, would be able to form new connections as well. Imec’s Jan Genoe, in a workshop organized by the European Union’s NeuRAM3 program, estimated that in a reconfigurable network with more than a hundred “neurons,” the reconfigurable interconnect components could dominate the circuit’s area, transistor count, and power consumption. Overall device footprint would be limited by via dimensions rather than transistor dimensions. Here, too, the need for 3D integration is clear.

Of the possible integration schemes that have been proposed, stacking of conventional circuits with through-silicon vias is the most mature, but supports relatively low interconnect density due to the large spacing of TSVs. Leti’s monolithic 3D-IC concept is intriguing, particularly when the NMOS and PMOS transistors may use different channel materials with incompatible processing requirements, but only envisions two stacked transistor layers. As an alternative, Genoe proposed adding thin-film transistors to existing interconnect stacks, with dimensions corresponding to the pitch of each layer. Achieving sufficient performance with silicon TFTs requires higher temperatures than conventional interconnect stacks can tolerate, but n-type metal-oxide semiconductors offer a promising combination of adequate performance and reasonable thermal budgets. Unfortunately, the performance of p-type metal-oxide semiconductors remains poor.

Neuromorphic computing is in its infancy. It’s difficult to say what the fundamental design components will be, much less the best way to assemble them. It’s already clear, though, that high speed, high density interconnects are essential for the data arrays being contemplated. Three-dimensional integration will be critical component of whatever designs ultimately emerge.

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