5 Issues Under The SPIE Radar

As usual, the recent SPIE Advanced Lithography Conference was a busy, if not an overwhelming, event. At the event, there were endless presentations on the usual subjects, such as design, patterning, metrology and photoresists.

And as in past years, one left the event with more questions than answers. At this year’s event, the most obvious question was (and still is) clear: Will extreme ultraviolet (EUV) lithography happen at 7nm–or at all? The answer: That’s still to be determined.

Besides the obvious subjects, there were five other questions, and issues, that went under the radar at SPIE. These are just a few of the issues to watch in the coming months or years:

1. The pellicles are coming! The pellicles are coming!

Obviously, EUV and the power source are a big deal. But at SPIE, litho expert Marc David Levenson uncovered the latest, and most intriguing, news about EUV–ASML announced that they are entering the EUV pellicle business.

This is a reverse from its previous position, as ASML once said it did not want to be in this business. Now, there seems to be no choice. EUV pellicles are a necessary part of the puzzle. Chipmakers do not want particles falling on an expensive mask in the EUV flow.

“If ASML is successful in commercializing EUV pellicles it will have removed an important barrier to EUVL adoption. Other challenges await,” Levenson wrote in a blog on Semiconductor Engineering.

2. Inspecting the details

Just how will chipmakers inspect EUV masks? At one time, the industry claimed it did not need an actinic wavelength inspection tool for EUV masks.

For now, the industry could make do with current optical tools to inspect EUV masks. But at some point, optical-based inspection may run out of gas, prompting the need for another technology. E-beam is a potential candidate.

Now, the industry is singing a different tune. Lithography engineering guru Mark Phillips from Intel urged the industry to develop an actinic mask inspection tool for EUV. The problem? It will require millions of dollars in R&D, and several years, to develop such a system. And will the industry fund a tool vendor to do it?

3. Has DSA hit a (big) speed bump?

At the last few SPIE events, there was a lot of hype for directed self-assembly (DSA). At this past event, there are a plethora of papers on the subject. But now, the problems are beginning to surface. And the question is will DSA find a place at 7nm and/or 5nm?

As before, the big problem with DSA is still defects. The industry has found ways to mitigate the defects in the process flow. But there is still a lack of suitable metrology tools in the market to find all of the problems.

Initially, though, DSA might find a way in the DRAM flow at the 1xnm node. But as one chipmaker put it, DSA is in a race with a rival technology–self-aligned double/quadruple patterning. For now, it’s not too difficult to figure out which technology is more mature.

4. New multi-beam efforts?

Multi-beam e-beam technology for direct-write lithography applications is still a long way from being realized in mass production.

Still, there are several efforts to watch for in the arena. First, Mapper Lithography is making incremental progress with its alpha multi-beam tool.

Second, at SPIE, IMS Nanofabrication discussed the status of its multi-beam tool for photomask production. No surprises there, but what was intriguing is that IMS discussed what it would take to develop a multi-beam tool for direct-write. It would require a significant jump in the power requirements, and of course, funding. Perhaps IMS was making its first pitch about the idea to the industry.

And as reported, KLA-Tencor recently put its multi-beam project on the shelf. But the technology, dubbed Rebl, is still alive. Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is taking the lead role in finding a suitable buyer for the technology, according to Burn Lin, vice president of R&D for the foundry giant. Stay tuned.

5. Natural selection

Intel is proposing a new patterning-like option—-selective deposition. Still in the R&D stage, selective deposition can be used to selectively deposit materials, namely metals on metals and dielectrics on dielectrics, on a device.

Thus far, selective deposition remains in the lab, mostly in universities. For its part, Intel hopes to generate interest in the industry about the technology. It hopes that fab tool vendors will start investing, and bring know-how, to the fledging technique. The jury is still out.