7nm Market Heats Up

GlobalFoundries rolls out 7nm finFET technology.


The 7nm finFET market is heating up in the foundry business amid the ongoing push to develop chips at advanced nodes.

Not long ago, TSMC announced plans to enter the 7nm finFET market. In addition, Intel and Samsung are also separately planning to enter the 7nm finFET race.

Now, GlobalFoundries is formally announcing its 7nm finFET technology. Slated for 2018, GlobalFoundries’ 7nm finFET process will be initially manufactured using 193nm immersion scanners, not extreme ultraviolet (EUV) lithography. The company plans to make an additional multi-billion dollar investment in its Fab 8 facility in New York to enable the development and production for 7nm finFETs.

Like its rivals, GlobalFoundries is also ramping up 14nm finFETs. But the company is taking a different strategy than its competitors at the next nodes. Unlike Intel, Samsung and TSMC—which plan to roll out finFETs at 10nm—GlobalFoundries is skipping 10nm and moving directly to 7nm.

“It’s our view that 10nm will be a short node,” said Sanjay Jha, chief executive at GlobalFoundries, at a press event.

Regarding 10nm, there is a difference of opinion in the market. Some view 10nm as a big node, while others see it as a half-step towards 7nm.

Still others see it differently. The 7nm node, according to officials at GlobalFoundries, will bring more benefits for customers in terms of performance, power and area scaling, as compared to 10nm. “(7nm is) the first scaled finFET node,” Jha said. “The industry is converging on 7nm finFET as the next long-lived node, which represents a unique opportunity for GlobalFoundries to compete at the leading edge.”

GlobalFoundries’ 7nm technology is expected to be ready for customer product design starts in the second half of 2017, with ramp to risk production in early 2018. Mass production is slated for the end of 2018.

Still, TSMC hopes to be the first player to ramp up 7nm. “Our 7nm technology development is well on track,” said Mark Liu, president and co-CEO of TSMC, in a recent conference call. “(Customers) all have aggressive product tape-out plans in the first half 2017, with volume production planned in early 2018.”

Samsung also plans to ship 7nm sometime in 2018. “Everyone is stating 2018 (for 7nm),” said G. Dan Hutcheson, chairman and chief executive of VLSI Research.

Still to be seen, however, is how many foundry customers will design 7nm finFET chips. Over time, fewer and fewer customers can afford to migrate to the next nodes amid soaring IC design and manufacturing costs. “There are fewer customers” Hutcheson said, “but the amount of design activity is pretty strong.”

Another option: FD-SOI
Still, there are foundry customers who will never move to finFETs. For those customers, GlobalFoundries is also developing fully-depleted silicon-on-insulator (FD-SOI) technology. More specifically, the company is developing planar 22nm FD-SOI, dubbed 22FDX.

GlobalFoundries has introduced an embedded magnetoresistive non-volatile memory technology (eMRAM) on its 22FDX platform. This eMRAM technology is designed for both code storage (flash) and working memory (SRAM) to enable ultra-efficient memory sub-systems that can be power cycled without any energy or performance penalty. The 22FDX eMRAM is a result of the company’s partnership with MRAM pioneer, Everspin Technologies.

While finFET-based technology is geared for high-end servers, graphics and related applications, 22nm FD-SOI is targeted for high-performance but lower power chips. “We believe that customers need to have a choice,” said Gary Patton, chief technology officer at GlobalFoundries.

Last week, the company extended its FD-SOI roadmap by rolling out a 12nm planar version of the technology. Compared to today’s finFETs, 12nm FD-SOI delivers a 15% performance boost and as much as 50% lower power consumption, according to GlobalFoundries.

Besides FD-SOI, GlobalFoundries will continue to ramp up 14nm finFETs, with 7nm finFETs in the pipeline. Compared to 14nm finFETs, GlobalFoundries’ 7nm finFETs will have 30% more performance with 60% lower power consumption, Patton said.

GlobalFoundries’ 7nm technology will incorporate several metal layers, copper interconnects and other features. In addition, the technology will be produced using 193nm immersion. The company will also incorporate design hooks at 7nm, which will enable the process to support EUV, if it is ready. “We will use EUV when it’s ready,” GlobalFoundries’ Jha said.

On the patterning front, GlobalFoundries’ strategy is somewhat similar to that of TSMC. TSMC is developing EUV at 7nm, but it hopes to insert EUV for mass production at 5nm. EUV will not be ready in time for TSMC’s 7nm node.

In contrast, Samsung hopes to insert EUV at 7nm. Samsung believes that 193nm immersion and multi-patterning are too complex and expensive at that node, prompting the need for EUV at 7nm. “Without EUV, the mask layers could explode,” said Kelvin Low, senior director of foundry marketing for Samsung, in a recent interview. “With EUV, we are talking about less mask layers.”

Intel, meanwhile, wants to insert EUV at 7nm, if it’s ready. If not, Intel will make finFETs at 7nm without it.

As before, the throughputs and uptimes are among the major issues with EUV. At present, ASML is upgrading its current EUV scanner from an 80-watt to a 125-watt source. This, in turn, will boost the throughputs to 85 wafers per hour (wph), up from 55 to 65 wph. But as before, chipmakers want EUV scanners with a 250-watt source to put the technology into mass production. This would enable a throughput of 125 wph.

There are other issues with EUV, such as the resists and mask infrastructure.

Related Stories
To 7nm And Beyond
7nm Lithography Choices
EUV: Cost Killer Or Savior?
Is EUV Making Progress?
Gaps Remain For EUV Masks
Resist Sensitivity, Source Power, And EUV Throughput
Next EUV Challenge: Mask Inspection


witeken says:

Do you know anything about the die shrink and gate pitch? Over at EETimes, they have published contradicting information: they say the shrink will be 30% compared to 14nm (which is not even close to the 50% shrink that a normal Moore’s Law die shrink would be, so die area would be even worse than TSMC 10nm), but they also say gate pitch will be 30nm, which is ridiculously low since Intel’s 10nm gate pitch is 54nm (and they scale 0.77x per generation).

memister says:

Can ASML really upgrade to 125W if the pellicle is not ready?

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