How a FOCoS chip production line that yielded over 99% was established, and higher integration complexity achieved to meet the growing needs of the 5G era.
The 5th Generation (5G) wireless systems popularity will push the package development into a high performance and heterogeneous integration form. For high I/O density and high performance packages, the promising Fan Out Chip on Substrate (FOCoS) provides a solution to match outsourced semiconductor assembly and testing (OSAT) capability. FOCoS is identified the Fan Out (FO) package, which can flip chips on a ball grid array substrate, and FOCoS constructs from multi-chips with short distance between chip to chip by multi-chip system for interposer less structure, which has the potential for heterogeneous integration and functional chip in one package. Heterogeneous integration refers to the integration of separately manufactured components into a higher level assembly. In this study, the yield of the production over 99% and of FOCoS chip last package was presented. To reduce the wafer warpage effect, we used three dimensional finite element method (3D-FEM) and advanced metrology analyzer (aMA) can find the optimum thickness and coefficient of thermal expansion (CTE) of the glass carrier. About FOCoS chip last device, large-size packages with 8 complex chips especially with fine line RDL and different size μbump joint structures inside have been successfully developed. In reliability examination, the test vehicle also passed the JEDEC and IPC qualification, respectively. Finally, ASE has successfully established the FOCoS chip production line, and further developed it in a larger area, and higher integration complexity to meet the growing needs of the 5G era.
Published in: 2020 IEEE 70th Electronic Components and Technology Conference (ECTC)
Authors: Jen-Kuang Fang, Min-Lung Huang, Hung-Jung Tu, Wen-Long Lu, and Peng Yang, all from Corporate R&D Center, Advanced Semiconductor Engineering Inc., Kaohsiung, Taiwan (R.O.C)
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