Advancements In Silicon Device Technology And Design Driving New SLM Monitor Categories

Silicon, the foundation of modern electronics, has seen continuous advancements since the early days of integrated circuits. The pace of innovation has been driven by the relentless quest for miniaturization, increased performance, and efficiency. However, Moore’s Law is no longer a given and silicon is facing functional limitations as technology scales. To address these challenges and continue scaling, exciting advancements are being made in both device technology and design types.

Innovations in device technology include gate-all-around (GAA) transistors, based on finFET structures but offering even greater control over the channel. This technology is poised to push the boundaries of scaling starting from 2nm, allowing for increased transistor density and improved performance. Heterogeneous integration combines different materials such as silicon and gallium nitride on the same chip, allowing for optimized performance and functionality. This approach is essential for developing next-generation power electronics and high-frequency devices.

Advanced device technology doesn’t help unless it’s possible to build the chips, and this required advancements in lithography. Extreme ultraviolet (EUV) lithography has been crucial for producing smaller and more intricate chip designs. This technique uses short-wavelength light to create incredibly fine patterns on silicon wafers, enabling the production of more complex and densely packed circuits, which translates to higher performance and lower power consumption.

In terms of new design types, monolithic system on chip (SoC) designs are increasingly being replaced by multi-die systems, where multiple chiplets are interconnected to achieve higher performance and functionality. Die-to-die (D2D) standards such as Universal Chiplet Interconnect Express (UCIe) are facilitating this shift. This approach allows for the integration of diverse functionalities, such as combining high-performance processors with specialized accelerators (e.g., for AI or graphics) in a single package.

Some new design types are even more revolutionary. Quantum computing uses quantum bits (qubits) to perform computations that are infeasible for classical computers. Research is ongoing into creating stable qubits and scalable quantum systems, with potential applications in cryptography, complex simulations, and more. Neuromorphic computing aims to mimic the neural structures and processing of the human brain. By designing silicon devices that operate like neural networks, researchers hope to create more efficient and adaptable computing systems. Neuromorphic chips have the potential to revolutionize fields such as artificial intelligence, robotics, and machine learning.

Despite the advancements in device technology and design styles, challenges remain. The physical limitations of silicon, such as problems with heat dissipation in 3D stacked structures and quantum effects, pose hurdles for further miniaturization. Reliability and service life become issues that chip designers need to address adequately. The complexity of modern chip designs requires sophisticated tools and methodologies for design and verification. One important solution is silicon lifecycle management (SLM) monitors, which can mitigate some of these challenges. There are several categories of SLM monitors in use today, including environmental, structural, functional, and physical.

Environmental sensors measure the most fundamental types of physical quantities in silicon for optimal performance, thermal management, and long-term reliability. Process detectors are used for capturing process related batch to batch, wafer to wafer, die to die, and on-chip variations during test. In the field, the sensors detect the effects of silicon aging, ensuring reliable operation and enabling predictive maintenance. They are also used for enabling dynamic voltage and frequency scaling (DVFS) for optimal chip performance while reducing power consumption.

Temperature sensors are critical and becoming even more so with the advent of 3D stacked structures and GAA transistors. Voltage monitors measure IR drop on the power network nets and include glitch detectors. Bursty workloads exhibited by applications such as AI processing can cause sudden spikes or glitches. Glitch detectors help avoid rejection of good dies during scan testing and prevent security side-channel attacks that use glitches to gain control of a chip.

Specialized in-silicon SLM monitors such as humidity and aging sensors are on the horizon and needed for better reliability, availability, and serviceability (RAS). This is especially important for automotive chips that operate under the harshest of environmental conditions (humidity and temperature extremes). Advanced driver assistance systems (ADAS) are responsible for the lives of drivers and passengers, so predictive maintenance before failure is essential.

Structural SLM monitors are used for safety, maintenance, and silicon health tracking. Types available today include:

• Memory test and repair: Monitors enable test, repair, and diagnostics for both on-chip and off-chip memories to maximize manufacturing yield. Test sequences can be initiated during production/manufacturing test, in-system during power on, or in mission mode for activities such as periodic testing.
• Logic built-in self-test (BIST) and repair: Structural monitors can be embedded within mission critical logic blocks and executed during manufacturing test, power on self-test (POST), in-system test, and in-system debug test.
• Monitor test and repair (MTR): Signal integrity monitors (SIMs) within physical layer (PHY) IP monitor the PHY “eye” margin integrity. These measurements can be accessed during POST, during PHY re-training, or in mission mode to monitor performance degradation for predictive maintenance. MTR can algorithmically test the D2D interconnect and perform multi-corner cumulative hard repair after swapping out “bad” or “marginal” UCIe lanes with spare/redundant ones.
• Lane test and repair (LTR): These monitors enable lane test and repair functionality for non-UCIe PHY based high volume, high data rate D2D lanes that feature redundancy. The real time reporting of lane health can be used for further analytics such as edge and fleet level.

Functional monitors provide new types of information in mission mode during both system level test and in-system test. Chip functions such as bus, memory, DMA, clock, processor, GPIO, and interrupt can be monitored to optimize performance and enhance longevity. Data collected from functional monitors over the silicon lifecycle can be leveraged by powerful analytics for improving the next generation of design.

SLM monitors can also help ensure security of chips in mission mode. Side-channel attacks—such as temperature, voltage glitching/brownouts and temperature variations—are becoming more sophisticated. These attack vectors can be used either singularly or collectively to gain access to chips. A combination of analog and digital security monitors provides peace of mind and saves costly reengineering work if security weaknesses are found. Embedding these monitors within silicon makes them extremely difficult to bypass, ensuring sustained security protection.

Synopsys provides all the SLM monitors listed above, as part of a comprehensive SLM solution. The Synopsys SLM STAR Memory System (SMS) enables MTR, Synopsys TestMAX XLBIST performs in-system self-test when functional safety is critical, the Synopsys SLM LTR IP solution provides lane test and repair, and Synopys PHY IP such as UCIe features integrated SIMs.

SLM monitors play an essential role in today’s designs. To keep pace with the ever-growing performance demands of cutting-edge applications such as artificial intelligence (AI), high performance computing (HPC), and automotive, device and system complexity continues to increase. The emergence of multi-die technology has compounded this complexity. To meet these demands, designers can optimize both the health and performance of their silicon by gathering meaningful data at each stage of the device lifecycle and from silicon to system that can provide actionable insights for intelligent decision making.