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AI Testing: Pushing Beyond DFT Architectures

The size of massive, highly parallel AI processor chips has a significant impact on design and test methodologies.

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Every day, more applications are deploying artificial intelligence (AI) system to increase automation beyond traditional systems. The continuous growth in computing demands of AI systems require designers to develop massive, highly parallel AI processor chips. Their large sizes and types of applications have a significant impact on their design and test methodologies. With thousands of repeated cores, along with IP integrated into one system-on-chip (SoC), new design-for-test (DFT) architectures and methodologies are needed to maximize silicon test quality while minimizing test costs. Furthermore, AI chips used in safety-critical applications, like autonomous driving, require the highest quality manufacturing test to achieve less than one defective-parts-per-million (DPPM) and need DFT structures to ensure the correct and safe functioning of the chips during system operation. However, adding such DFT logic to the design further increases the size of already large chips.

Leveraging a hierarchical test methodology is ideal for AI designs. It employs a divide-and-conquer approach by dividing the design into smaller hierarchical partitions for DFT sign-off which includes the following: DFT insertion, test mode setup, pattern generation and verification. An AI design can contain multiple levels of hierarchy, each with repeated DFT partitions, and each partition could be a single core or a group of cores depending on the DFT architecture as shown in Figure 1. With a hierarchical test methodology, DFT sign-off for every unique partition at a hierarchical level is performed only once and reused in all replicated instances. The exact process is repeated at each hierarchical level to achieve the DFT sign-off for the entire design as shown in Figure 2. After completing the DFT at the partition level, the corresponding test mode setup and patterns are ported to the chip level to enable application with an automatic test equipment (ATE).


Fig. 1: Typical AI chip showing DFT partitions at different hierarchical levels.


Fig. 2: Hierarchical test enables DFT sign-off and reuse of partitions at each hierarchical level.

One of the most notable advantages of this methodology is significantly increased productivity and reduced compute resource requirements. This is because the DFT sign-off task for each unique partition can be performed independently and in parallel with other partitions, using much smaller compute machines than needed for flat DFT sign-off methodology, as depicted in figure 3.


Fig. 3: Increased productivity and reduced compute resources with hierarchical test methodology.

In general, AI test requirements often conflict with stringent power, performance and area (PPA) requirements. With discrete test flows, the DFT logic is generated and added into the design logic without considering its impact on the physical design (PD), and the DFT logic is analyzed similarly to any other functional logic for implementation during the PD process. This lack of DFT logic awareness in physical design implementation technology often results in degraded PPA for the entire design (user plus DFT logic) or significant delay in achieving design convergence. In some cases, a DFT architecture change is required for resolving these issues. The degradation becomes more pronounced in the case of AI designs because a sub-optimal DFT logic implementation in a core, compounded when replicated across thousands of cores, severely impacts the PPA of the entire chip.


Fig. 4: Outdated, discrete test flow with isolated DFT and physical design process.

For these large and complex AI chips, it is easy to understand that just as the DFT architecture and methodologies are important to meet test goals, DFT implementation that is physically-aware is crucial to minimize the burden on the physical design effort to achieve optimal PPA. Hence, the AI chip designers must deploy test technology that addresses the combined challenges of optimal DFT architecture and optimal implementation concurrently.

Effective and efficient test solutions must optimize the physical implementation of DFT logic to realize the full benefits of suitable test methodologies and architectures for AI designs. In addition to supporting hierarchical test, advanced DFT technologies unify DFT and physical implementation engines into one seamless flow for physically-aware design and DFT implementation. Some of the important techniques used by such test solutions include:

Targeted logical and physical optimizations of DFT logic such as automatic distribution of test compression block for placement, intelligent routing of DFT logic, re-clustering of test compression connections, clock network optimizations, etc.


Fig. 5: High scan compression with congestion optimization (heat map).

Location-aware test points for improved routing and reduced pattern count.


Fig. 6: Traditional test points vs. location aware test points.

Location based ordering of scan chain elements to reduce congestion.


Fig. 7: Congestion with scan cells stitching without and with physical information.

Physically-aware wrapper cells based on the location of core pins during isolation wrapper insertion.

As test goals to achieve high-quality, low cost testing of AI chips become increasingly challenging, test solutions must include physically-aware DFT implementation to enable ideal architectures, time-saving methodologies, and optimal PPA. Applying discrete DFT technologies and flows detached from today’s implementation technology invites sub-par results or an enormous amount of effort to compensate. Advanced test technologies that address the challenges of DFT and physical implementation as one unified goal are needed to keep up with the growing expectations of todays’ design and test teams.



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